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ps022815-0206 zilog worldwide headquarters ? 532 race street ? san jose, ca 95126-3432 telephone: 408.558.8500 ? fax: 408.558 .8300 ? www.zilog.com product specification high-performance 8-b it microcontrollers z8 encore! xp ? 4k series
ps022815-0206 this publication is subject to replacement by a later edition. to determine whether a later edition exists, or to reques t copies of publications, contact: zilog worldwide headquarters 532 race street san jose, ca 95126 telephone: 408.558.8500 fax: 408.558.8300 www.zilog.com document disclaimer zilog is a registered trademark of zilog inc. in th e united states and in other countries. all other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. ?2005 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. devices sold by zilog, inc. are covered by warranty and limitation of liability provisions a ppearing in the zilog, inc. terms and conditions of sale. zilog, inc. makes no warranty of merchantabi lity or fitness for any purpose except with the express written approval of zilog, use of informati on, devices, or technology as critical components of life support systems is not authorized. no licens es are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
ps022815-0206 z8 encore! xp ? 4k series product specification iii revision history each instance in the following table reflects a change to this document from its previous revision. to see more detail, click the appropriate link in the table. revision history of this document date revision level description november 2004 07 minor corrections made throughout document. major changes include adding timer caution note in the timer chapter and fl ash controller caution note in the flash memory chapter. in the ordering chapter, corrected nvds size typo. added three new cpu instructions. added 20-pin soic package drawing in packaging chapter. changed wdt oscillator frequ ency to 10 khz in the oscillator control chapter. clarified nvds read/write operations in the nvds code interface section. december 2004 08 minor corrections to low-power modes, general purpose i/o, analog to digital converter, comparator, flas h option bits, internal precision oscillator, and electrical characteristics chapters. 31,39, 118,119,1 20,143,14 5,146,177, 202,203 january 2005 09 added 8-pin development kit and usb smart cable accessory kit ordering information. 227 may 2005 10 added clarifying information for using the uart baud rate generator as a simplified timer. removed 2.2v ref in table 129. changed vbo to lvd in interrupt controller. ch anged pa5 t1out to t1out and added clarification of ports a- c for 8-pin and 20/28 pin devices in tables 21, 26 and 27 in the gpio. changed t por and t smr typical values in table 125, and endurance minimum value in table 126 in electrical characteristics. removed 2.2v refere nce in electrical characteristics and analog-to-digital converter chapt ers. added clarifying text when writing to the flash control register in flash memory chapter. added lead-free packaging order information 99, 129,39,50, 51,56,58, 59,61,43, 46,203, 204,206, 121,123, 126-140, 222-228 june 2005 11 inserted missing temperature sens or chapter. updated figure1 to include transimpedance amplifier. added transimpedance amplifer to feature description. removed reference to vbo enable. updated table 124 format. changed temperature sensor column in ordering information pages. 3, 5, 152, 223, 227
ps022815-0206 z8 encore! xp ? 4k series product specification iv october 2005 12 added references to optional low-power operational amplifier and removed references to transimpedance amplifier. numerous other small corrections throughout the book. 1-6, 8-12, 14-15, 17. 19, 21-22, 24-27, 29- 31, 32-40, 44, 46, 48, 57-59, 62, 67-69, 72- 73, 75-76, 78, 81-89, 99-100, 102, 104- 105, 112- 125, 129- 140, 142- 144, 146- 151, 172- 177, 182, 204-223, 231, 237- 244 november 2005 13 reverted back to version 11, removing changes in version 12. updated flash option bits chapter. 142-154 december 2005 14 restored version 12 changes and rectified elements to incorporate version 11 updates. 8, 84, 87, 88, 113, 124, 126, 148-161, 216, 218, 220, 221 february 2006 15 updated for 8-pin qfn/mlf-s in table 2, figure 2, and packaging section. updated uart features. 7, 8, 89 revision history of this document date revision level description
ps022815-0206 table of contents z8 encore! xp ? 4k series product specification v table of contents revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xv overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 cpu and peripheral overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ez8 cpu features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 general purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 non-volatile data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10-bit analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 low-power operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 low battery detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ps022815-0206 table of contents z8 encore! xp ? 4k series product specification vi program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 reset, stop mode recovery and low voltage detection . . . . . . . . . . . . . . . . 20 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 voltage brown-out reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 watch-dog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 external reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 external reset indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 on-chip debugger initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 stop mode recovery using watch-dog timer time-out . . . . . . . . . . . . . 26 stop mode recovery using a gpio port pi n transition . . . . . . . . . . . . . . 26 stop mode recovery using the external r eset pin . . . . . . . . . . . . . . . . 27 low voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 reset register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 peripheral-level power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 power control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 gpio port availability by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 gpio alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 direct led drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 shared reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 shared debug pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 crystal oscillator override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5v tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ps022815-0206 table of contents z8 encore! xp ? 4k series product specification vii external clock setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 gpio control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 port a?d address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 port a?d control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 port a?d data direction sub-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 port a?d alternate function sub-registers . . . . . . . . . . . . . . . . . . . . . . . . 42 port a?c input data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 port a?d output data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 led drive enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 led drive level high register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 led drive level low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 interrupt vector listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 master interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 interrupt vectors and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 software interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 interrupt control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 interrupt request 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 interrupt request 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 interrupt request 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 irq0 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 57 irq1 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 58 irq2 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 59 interrupt edge select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 shared interrupt select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 reading the timer count values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 timer pin signal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ps022815-0206 table of contents z8 encore! xp ? 4k series product specification viii timer 0?1 high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 timer reload high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . 76 timer 0-1 pwm high and low byte registers . . . . . . . . . . . . . . . . . . . . . . 77 timer 0?1 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 watch-dog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 watch-dog timer refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 watch-dog timer time-out response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 watch-dog timer reload unlock sequence . . . . . . . . . . . . . . . . . . . . . . . . 85 watch-dog timer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 watch-dog timer control register definitions . . . . . . . . . . . . . . . . . . . . . . 86 watch-dog timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 watch-dog timer reload upper, high and low byte registers . . . . . . . . . 87 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 transmitting data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . 91 transmitting data using the interrupt-driven method . . . . . . . . . . . . . . . . . 92 receiving data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . . . 93 receiving data using the interrupt-driven method . . . . . . . . . . . . . . . . . . . 94 clear to send (cts) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 multiprocessor (9-bit) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 external driver enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 uart baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 uart control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 uart transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 uart receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 uart status 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 uart status 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 uart control 0 and control 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . 103 uart address compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 uart baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . 106 infrared encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
ps022815-0206 table of contents z8 encore! xp ? 4k series product specification ix architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 transmitting irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 receiving irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 infrared encoder/decoder control register definitions . . . . . . . . . . . . . . 112 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 automatic powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 single-shot conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 programmable trigger point alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 calibration and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 adc compensation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 input buffer stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 low-power operational amplifier (lpo) . . . . . . . . . . . . . . . . . . . . . . . . . . 123 adc control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 adc control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 adc control/status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 adc data high byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 adc data low bits register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 adc high threshold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 adc low threshold register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 comparator control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 131 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 temperature sensor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
ps022815-0206 table of contents z8 encore! xp ? 4k series product specification x flash operation timing using the flash frequency registers . . . . . . . . . 140 flash code protection against external access . . . . . . . . . . . . . . . . . . . . 140 flash code protection against accidental program and erasure . . . . . . . 140 byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 page erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 mass erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 flash controller bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 flash controller behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . . 143 flash control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 flash page select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 flash sector protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 flash frequency high and low byte registers . . . . . . . . . . . . . . . . . . . . 147 flash option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 option bit configuration by reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 option bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 reading the flash information page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 flash option bit control register definitions . . . . . . . . . . . . . . . . . . . . . . 150 trim bit address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 trim bit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 flash option bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 flash program memory address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . 151 flash program memory address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . 152 trim bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 trim bit address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 trim bit address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 trim bit address 0002h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 trim bit address 0003h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 trim bit address 0004h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 zilog calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 adc calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 watchdog timer calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 serialization data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 randomized lot identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 temperature sensor calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 non-volatile data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
ps022815-0206 table of contents z8 encore! xp ? 4k series product specification xi overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 nvds code interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 power failure protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 optimizing nvds memory usage for execution speed . . . . . . . . . . . . . . 165 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 ocd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 ocd auto-baud detector/generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 ocd serial errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 ocd unlock sequence (8-pin devices only) . . . . . . . . . . . . . . . . . . . . . . 171 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 runtime counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 on-chip debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 on-chip debugger control register definitions . . . . . . . . . . . . . . . . . . . . 177 ocd control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 ocd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 oscillator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 system clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 clock failure detection and recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 oscillator control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 crystal oscillator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 oscillator operation with an ex ternal rc network . . . . . . . . . . . . . . . . . . 187 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
ps022815-0206 table of contents z8 encore! xp ? 4k series product specification xii ez8 cpu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 assembly language programming introduction . . . . . . . . . . . . . . . . . . . . 191 assembly language syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 ez8 cpu instruction notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 ez8 cpu instruction classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 opcode maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 on-chip peripheral ac and dc electrical characteristics . . . . . . . . . . . . 219 general purpose i/o port input data sample timing . . . . . . . . . . . . . . . . 224 general purpose i/o port output timing . . . . . . . . . . . . . . . . . . . . . . . . . 226 on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 customer feedback form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
ps022815-0206 list of figures z8 encore! xp ? 4k series product specification xiii list of figures figure 1. z8 encore! xp ? 4k series block diagram . . . . . . . . . . . . . . . . . . . . . 3 figure 2. z8f04xa, z8f02xa, and z8f01xa in 8-pin soic, qfn/mlf-s, or pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. z8f04xa, z8f02xa, and z8f01xa in 20-pin soic, ssop or pdip pack- age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. z8f04xa, z8f02xa, and z8f01xa in 28-pin soic, ssop or pdip pack- age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. power-on reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6. voltage brown-out reset operation . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. gpio port pin block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 8. interrupt controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 9. timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 10. uart block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 11. uart asynchronous data format without parity . . . . . . . . . . . . . . 91 figure 12. uart asynchronous data format with parity . . . . . . . . . . . . . . . . . 91 figure 13. uart asynchronous multipr ocessor mode data format . . . 95 figure 14. uart driver enable signal timi ng (shown with 1 stop bit and parity) 97 figure 15. uart receiver interrupt service rout ine flow . . . . . . . . . . . . . . . . 99 figure 16. infrared data communication system block diagram . . . . . . . . . 109 figure 17. infrared data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 18. irda data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 19. analog-to-digital converter block diagram . . . . . . . . . . . . . . . . . . 114 figure 20. comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 figure 21. flash memory arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 22. flash controller operation flow chart . . . . . . . . . . . . . . . . . . . . . . 139 figure 23. on-chip debugger block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 24. interfacing the on-chip debugger ?s dbg pin with an rs-232 interface (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
ps022815-0206 list of figures z8 encore! xp ? 4k series product specification xiv figure 25. interfacing the on-chip debugger ?s dbg pin with an rs-232 interface (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 26. ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 27. recommended 20 mhz crystal oscill ator configuration . . . . . . . . 186 figure 28. connecting the on-chip oscillator to an external rc network . . . 188 figure 29. typical rc oscillator frequency as a function of the external capaci- tance with a 45kohm resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 30. opcode map cell description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 31. first opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 figure 32. second opcode map after 1fh . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 33. typical active mode idd versus system clock frequency . . . . . . 216 figure 34. port input sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 figure 35. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 figure 36. on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 figure 37. uart timing with cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 figure 38. uart timing without cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 figure 39. 8-pin plastic dual inline package (pdip) . . . . . . . . . . . . . . . . . . . 230 figure 40. 8-pin small outline integrated ci rcuit package (soic) . . . . . . . . 231 figure 41. 8-pin quad flat no-lead package (qfn)/ mlf-s . . . . . . . . . . . . 232 figure 42. 20-pin plastic dual inline package (pdip) . . . . . . . . . . . . . . . . . . 233 figure 43. 20-pin small outline integrated circuit package (soic) . . . . . . . . 234 figure 44. 20-pin small shrink outline package (ssop) . . . . . . . . . . . . . . . . 235 figure 45. 28-pin plastic dual inline package (pdip) . . . . . . . . . . . . . . . . . . 236 figure 46. 28-pin small outline integrated circuit package (soic) . . . . . . . . 237 figure 47. 28-pin small shrink outline package (ssop) . . . . . . . . . . . . . . . . 238
ps022815-0206 list of tables z8 encore! xp ? 4k series product specification xv list of tables table 1. z8 encore! xp ? 4k series family part selection guide . . . . . . . . . . . . 2 table 2. z8 encore! xp ? 4k series package options. . . . . . . . . . . . . . . . . . . . . 7 table 3. signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. pin characteristics (20- and 28-pin devi ces) . . . . . . . . . . . . . . . . . . . . 11 table 5. pin characteristics (8-pin devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. z8 encore! xp ? 4k series series program memory maps . . . . . . . . . 14 table 7. z8 encore! xp ? 4k series flash memory information area map . . . . 15 table 8. register file address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. reset and stop mode recovery characteristics and latency. . . . . . 21 table 10. reset sources and resulting reset type . . . . . . . . . . . . . . . . . . . . . 22 table 11. stop mode recovery sources and resulting action . . . . . . . . . . . . 26 table 12. reset status register (rststat). . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. power control register 0 (pwrctl0). . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. port availability by device and package type . . . . . . . . . . . . . . . . . . 32 table 15. port alternate function mapping (non 8-pin parts) . . . . . . . . . . . . . . 36 table 16. port alternate function mapping (8-pin parts). . . . . . . . . . . . . . . . . . 39 table 17. gpio port registers and sub-registers . . . . . . . . . . . . . . . . . . . . . . 40 table 18. port a?d gpio address registers (pxaddr). . . . . . . . . . . . . . . . . . 41 table 19. port a?d control registers (pxctl) . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 20. port a?d data direction sub-registers (pxdd) . . . . . . . . . . . . . . . . 42 table 21. port a?d alternate function sub-registers (pxaf). . . . . . . . . . . . . . 43 table 22. port a?d output control sub-registers (pxoc) . . . . . . . . . . . . . . . . 43 table 23. port a?d high drive enable sub-registers (pxhde) . . . . . . . . . . . . 44 table 24. port a?d stop mode recovery source enable sub-registers (px- smre) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 25. port a?d pull-up enable sub-register s (pxpue) . . . . . . . . . . . . . . . 45 table 26. port a?d alternate function set 1 sub-registers (pxafs1). . . . . . . 45 table 27. port a?d alternate function set 2 sub-registers (pxafs2). . . . . . . 46
ps022815-0206 list of tables z8 encore! xp ? 4k series product specification xvi table 28. port a?c input data registers (pxin) . . . . . . . . . . . . . . . . . . . . . . . . 46 table 29. port a?d output data register (pxout). . . . . . . . . . . . . . . . . . . . . . 47 table 30. led drive enable (leden) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 31. led drive level high register (ledlvlh) . . . . . . . . . . . . . . . . . . . . 48 table 32. led drive level low register (ledlvll). . . . . . . . . . . . . . . . . . . . . 48 table 33. trap and interrupt vectors in order of priority . . . . . . . . . . . . . . . . . . 51 table 34. interrupt request 0 register (irq0) . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 35. interrupt request 1 register (irq1) . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 36. interrupt request 2 register (irq2) . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 37. irq0 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 38. irq0 enable high bit register (irq0enh) . . . . . . . . . . . . . . . . . . . . 57 table 39. irq0 enable low bit register (irq0enl). . . . . . . . . . . . . . . . . . . . . 57 table 40. irq1 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 41. irq1 enable high bit register (irq1enh) . . . . . . . . . . . . . . . . . . . . 58 table 42. irq1 enable low bit register (irq1enl). . . . . . . . . . . . . . . . . . . . . 59 table 43. irq2 enable and priority encoding . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 44. irq2 enable high bit register (irq2enh) . . . . . . . . . . . . . . . . . . . . 59 table 45. irq2 enable low bit register (irq2enl). . . . . . . . . . . . . . . . . . . . . 60 table 46. interrupt edge select register (irqes). . . . . . . . . . . . . . . . . . . . . . . 60 table 47. shared interrupt select register (irqss) . . . . . . . . . . . . . . . . . . . . . 61 table 48. interrupt control register (irqctl) . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 49. timer 0?1 high byte register (txh) . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 50. timer 0?1 low byte register (txl) . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 51. timer 0?1 reload high byte register (txrh) . . . . . . . . . . . . . . . . . . 77 table 52. timer 0?1 reload low byte register (txrl). . . . . . . . . . . . . . . . . . . 77 table 53. timer 0?1 pwm high byte register (txpwmh) . . . . . . . . . . . . . . . . 77 table 54. timer 0?1 control register 0 (txctl0) . . . . . . . . . . . . . . . . . . . . . . . 78 table 55. timer 0?1 pwm low byte register (txpwml) . . . . . . . . . . . . . . . . . 78 table 56. timer 0?1 control register 1 (txctl1) . . . . . . . . . . . . . . . . . . . . . . . 79 table 57. watch-dog timer approximate time-out delays . . . . . . . . . . . . . . . 84
ps022815-0206 list of tables z8 encore! xp ? 4k series product specification xvii table 58. watch-dog timer control register (wdtctl) . . . . . . . . . . . . . . . . . 86 table 59. watch-dog timer reload upper byte register (wdtu) . . . . . . . . . . 87 table 60. watch-dog timer reload high byte register (wdth) . . . . . . . . . . . 87 table 61. watch-dog timer reload low byte register (wdtl) . . . . . . . . . . . . 88 table 62. uart transmit data register (u0txd) . . . . . . . . . . . . . . . . . . . . . 100 table 63. uart receive data register (u0rxd) . . . . . . . . . . . . . . . . . . . . . . 101 table 64. uart status 0 register (u0stat0) . . . . . . . . . . . . . . . . . . . . . . . . 101 table 65. uart status 1 register (u0stat1) . . . . . . . . . . . . . . . . . . . . . . . . 103 table 66. uart control 0 register (u0ctl0). . . . . . . . . . . . . . . . . . . . . . . . . 103 table 67. uart control 1 register (u0ctl1). . . . . . . . . . . . . . . . . . . . . . . . . 104 table 68. uart address compare register (u0addr) . . . . . . . . . . . . . . . . . 106 table 69. uart baud rate high byte register (u0brh) . . . . . . . . . . . . . . . . 106 table 70. uart baud rate low byte register (u0brl) . . . . . . . . . . . . . . . . 106 table 71. uart baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 72. adc control register 0 (adcctl0) . . . . . . . . . . . . . . . . . . . . . . . . 124 table 73. adc control/status register 1 (adcctl1). . . . . . . . . . . . . . . . . . . 126 table 74. adc data high byte r egister (adcd_h) . . . . . . . . . . . . . . . . . . . . 127 table 75. adc data low bits register (adcd_l). . . . . . . . . . . . . . . . . . . . . . 127 table 76. adc high threshold high byte (adcthh) . . . . . . . . . . . . . . . . . . . 128 table 77. adc low threshold high byte (adctlh). . . . . . . . . . . . . . . . . . . . 128 table 78. comparator control register (cmp0) . . . . . . . . . . . . . . . . . . . . . . . 131 table 79. z8 encore! xp? 4k series flash memory configurations . . . . . . . . 136 table 80. flash code protection using the flash option bits . . . . . . . . . . . . . 141 table 81. flash control register (fctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 82. flash status register (fstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 83. flash page select register (fps) . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 84. flash sector protect register (fprot). . . . . . . . . . . . . . . . . . . . . . 146 table 85. flash frequency high byte register (ffreqh) . . . . . . . . . . . . . . . 147 table 86. flash frequency low byte register (ffreql). . . . . . . . . . . . . . . . 147 table 87. trim bit address register (trmadr) . . . . . . . . . . . . . . . . . . . . . . . 150
ps022815-0206 list of tables z8 encore! xp ? 4k series product specification xviii table 88. trim bit data register (trmdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 89. flash option bits at program memory address 0000h . . . . . . . . . . 151 table 90. flash options bits at program memory address 0001h . . . . . . . . . 152 table 91. trim options bits at address 0000h . . . . . . . . . . . . . . . . . . . . . . . . 153 table 92. trim option bits at 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 93. trim option bits at 0002h (tipo) . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 94. trim option bits at address 0003h (tlvd) . . . . . . . . . . . . . . . . . . . 154 table 95. trim option bits at 0004h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 96. adc calibration bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 97. adc calibration data location . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 98. watchdog calibration high byte at 007eh (wdtcalh) . . . . . . . . . 158 table 99. watchdog calibration low byte at 007fh (wdtcall). . . . . . . . . . 158 table 100. serial number at 001c - 001f (s_num) . . . . . . . . . . . . . . . . . . . . 159 table 101. serialization data locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 102. lot identification number (rand_lot). . . . . . . . . . . . . . . . . . . . . 159 table 103. randomized lot id locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 104. temperature sensor calibration high byte at 003a (tscalh). . . 162 table 105. temperature sensor calibration low byte at 003b (tscall) . . . 162 table 106. write status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 107. nvds read time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 108. ocd baud-rate limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 109. ocd control register (ocdctl) . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 110. ocd status register (ocdstat) . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 111. oscillator configurati on and selection . . . . . . . . . . . . . . . . . . . . . . 181 table 112. oscillator control r egister (oscctl) . . . . . . . . . . . . . . . . . . . . . . 183 table 113. recommended crystal oscillator s pecifications. . . . . . . . . . . . . . 186 table 114. transconductance values for low, medium, and high gain operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 115. assembly language syntax example 1. . . . . . . . . . . . . . . . . . . . . 192 table 116. assembly language syntax example 2. . . . . . . . . . . . . . . . . . . . . 192 table 117. notational shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
ps022815-0206 list of tables z8 encore! xp ? 4k series product specification xix table 118. additional symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 119. arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 120. bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 121. block transfer instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 122. cpu control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 123. logical instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 124. load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 table 125. program control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 126. rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 127. ez8 cpu instruction summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 128. opcode map abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 129. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 130. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 131. power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 132. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 table 133. internal precision oscillator electr ical characteristics . . . . . . . . . . 218 table 134. power-on reset and voltage brow n-out electrical characteristics and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 135. flash memory electrical characteristics and timing . . . . . . . . . . . 220 table 136. watch-dog timer electrical charac teristics and timing . . . . . . . . 220 table 137. analog-to-digital converter el ectrical characteristics and timing. 221 table 138. non volatile data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 139. low power operational amplifer el ectrical characteristics . . . . . . 223 table 140. comparator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 223 table 141. temperature sensor electrical characteristics . . . . . . . . . . . . . . . 224 table 142. gpio port input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table 143. gpio port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table 144. on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 145. uart timing with cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 146. uart timing without cts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
ps022815-0206 overview z8 encore! xp ? 4k series product specification 1 overview the z8 encore! ? mcu family of products are the first in a line of zilog ? microcontrol- ler products based upon the 8-bit ez8 cpu. the z8 encore! xp ? 4k series products expand upon zilog?s extensive line of 8-bit microcontrollers. the flash in-circuit pro- gramming capability allows for faster develo pment time and program ch anges in the field. the new ez8 cpu is upward compatible with existing z8 ? instructions. the rich periph- eral set of the z8 encore! xp ? 4k series makes it suitable for a variety of applications including motor control, secur ity systems, home appliances, personal electronic devices, and sensors. features ? 20 mhz ez8 cpu ? 1kb, 2kb or 4kb flash memory wi th in-circuit programming capability ? 256b, 512b or 1kb register ram ? 16b to 128b non-volatile data storage (nvds) ? up to 20 vectored interrupts ? 6 to 25 i/o pins depending upon package ? internal precision oscillator ? external crystal oscillator ? full-duplex uart ? the uart baud rate generato r (brg) can be configured and used as a basic 16-bit timer ? infrared data association (ir da)-compliant infrared encode r/decoders, integrated with uart ? two enhanced 16-bit timers with ca pture, compare, and pwm capability ? watch-dog timer (wdt) with dedi cated internal rc oscillator ? on-chip debugger ? optional 8-channel, 10-bit anal og-to-digital converter (adc) ? optional on-chip temperature sensor ? on-chip analog comparator ? optional on-chip low-power ope rational amplifier (lpo) ? voltage brown-out protection (vbo)
ps022815-0206 overview z8 encore! xp ? 4k series product specification 2 ? programmable low battery detectio n (lvd) (8-pin devices only) ? bandgap generated precision voltage referenc es available for the adc, comparator, vbo, and lvd. ? power-on reset (por) ? 2.7 v to 3.6 v operating voltage ? up to thirteen 5v-tolerant input pins ? 8-, 20- and 28-pin packages ? 0 to +70c and -40 to +105c for operating temperature ranges part selection guide table 1 identifies the basic features and package st yles available for each device within the z8 encore! xp ? 4k series product line. note: * advanced analog includes adc, temper ature sensor, and low-power operational amplifer. block diagram figure 1 illustrates the block diagram of th e architecture of the z8 encore! xp ? 4k series devices . table 1. z8 encore! xp ? 4k series family part selection guide part number flash (kb) ram (b) eeprom (b) i/o comparator advanced analog* adc inputs packages z8f042a 4 1024 128 6?23 yes yes 4?8 8-, 20- and 28-pins Z8F041A 4 1024 128 6?25 yes no 0 8-, 20- and 28-pins z8f022a 2 512 64 6?23 yes yes 4?8 8-, 20- and 28-pins z8f021a 2 512 64 6?25 yes no 0 8-, 20- and 28-pins z8f012a 1 256 16 6?23 yes yes 4?8 8-, 20- and 28-pins z8f011a 1 256 16 6?25 yes no 0 8-, 20- and 28-pins
ps022815-0206 overview z8 encore! xp ? 4k series product specification 3 figure 1. z8 encore! xp ? 4k series block diagram gpio irda uart timers adc and flash flash controller ram ram controller memory interrupt controller on-chip debugger ez8 cpu wdt por/vbo & reset controller xtal/rc oscillator register bus memory busses system clock comparator temperature sensor nvds controller low power rc oscillator internal oscillator control oscillator precision lpo
ps022815-0206 overview z8 encore! xp ? 4k series product specification 4 cpu and peripheral overview ez8 cpu features the ez8 cpu, zilog ? ?s latest 8-bit central processing unit (cpu), meets the continuing demand for faster and more code-efficient microcontrollers. the ez8 cpu executes a superset of the original z8 ? instruction set. the ez8 cpu features include: ? direct register-to-register architecture allows each register to function as an accumulator, improving execution time and d ecreasing the required program memory ? software stack allows much greater dept h in subroutine calls and interrupts than hardware stacks ? compatible with existing z8 ? code ? expanded internal register file allows access of up to 4kb ? new instructions improve execution efficiency for code developed using higher-level programming languages, including c ? pipelined instruction fetch and execution ? new instructions for improv ed performance including bit, bswap, btj, cpc, ldc, ldci, lea, mult, and srl ? new instructions support 12-bit linea r addressing of the register file ? up to 10 mips operation ? c-compiler friendly ? 2 to 9 clock cycles per instruction for more information regardin g the ez8 cpu, refer to the ez8 cpu user manual avail- able for download at www.zilog.com . general purpose i/o the z8 encore! xp ? 4k series features 6 to 25 port pins (ports a?d) for general purpose i/o (gpio). the number of gpio pins available is a function of package. each pin is indi- vidually programmable. flash controller the flash controller programs and erases fl ash memory. the flash controller supports several protection mechanisms against accidental program and erasure.
ps022815-0206 overview z8 encore! xp ? 4k series product specification 5 non-volatile data storage the non-volatile data storage (nvds) uses a h ybrid hardware/softwar e scheme to imple- ment a byte programmable data memory and is capable of over 100,000 write cycles. internal precision oscillator the internal precision oscillator (ipo) is a tr immable clock source that requires no exter- nal components. crystal oscillator the crystal oscillator circuit pr ovides highly accurate clock fre quencies with the use of an external crystal, ceramic resonator or rc network. 10-bit analog-to-dig ital converter the optional analog-to-digital co nverter (adc) converts an analog input signal to a 10-bit binary number. the adc accepts inputs from eigh t different analog input pins in both sin- gle-ended and differential modes. the adc also features a unity gain buffer when high input impedance is required. low-power operational amplifier the optional low-power operatio nal amplifier (lpo) is a gene ral-purpose amplifier prima- rily targeted for current sense applications. the lpo output may be rout ed internally to the adc or externally to a pin. analog comparator the analog comparator compares the signal at an input pin with either an internal pro- grammable voltage reference or a second input pin. the comparat or output can be used to drive either an output pin or to generate an interrupt. temperature sensor the optional temperature sensor produces an analog output proportional to the device temperature. this signal can be sent to either the adc or the analog comparator.
ps022815-0206 overview z8 encore! xp ? 4k series product specification 6 low battery detector the low battery detector (lvd) is able to ge nerate an interrupt wh en the supply voltage drops below a user-programmable level. th e lvd is available on 8-pin devices only. uart the uart is full-duplex and capable of handling asynchronous data transfers. the uart supports 8- and 9-bit data modes and select able parity. the uart also supports multi- drop address processing in hardware. the uart baud rate generator (brg) can be config- ured and used as a basic 16-bit timer. timers two enhanced 16-bit reloadable timers can be used for timing/counting events or for motor control operations. these timers provid e a 16-bit programmable reload counter and operate in one-shot, continuous, gated, capture, capture restart, compare, capture and compare, pwm single output and pwm dual output modes. interrupt controller the z8 encore! xp ? 4k series products support up to 20 interrupts. these interrupts con- sist of 8 internal peripheral interrupts and 12 general-purpose i/o pin interrupt sources. the interrupts have 3 levels of programmable interrupt priority. reset controller the z8 encore! xp ? 4k series products can be reset using the reset pin, power-on reset, watch-dog timer (wdt) time-out, stop mode exit, or voltage brown-out (vbo) warning signal. the reset pin is bi-directional, meaning it functions as reset source as well as a reset indicator. on-chip debugger the z8 encore! xp ? 4k series products feature an integrated on-chip debugger (ocd). the ocd provides a rich set of debugging ca pabilities, such as re ading and writing regis- ters, programming flash memory, setting break points and executing code. a single-pin interface provides comm unication to the ocd.
ps022815-0206 pin description z8 encore! xp ? 4k series product specification 7 pin description overview the z8 encore! xp ? 4k series products are available in a variety of packages styles and pin configurations. this chapter describes the signals and available pin configurations for each of the package styles. for information re garding the physical p ackage specifications, refer to the chapter packaging on page 230 . available packages table 2 identifies the package styles that are ava ilable for each device in the z8 encore! xp ? 4k series product line. pin configurations figures 2 through figures 4 illustrate the pin configurations for all of the packages avail- able in the z8 encore! xp ? 4k series. refer to table 3 for a description of the signals. the analog input alternate functions (ana x ) are not available on the Z8F041A, z8f021a, and z8f011a devices. the analog supply pins (av dd and av ss ) are also not available on these parts, and are replaced by pb6 and pb7. at reset, all port a, b and c pins default to an input state. in add ition, any alternate func- tionality is not enabled, so the pins func tion as general purpose input ports until pro- grammed otherwise. at powerup, the port d0 pin defaults to the reset alternate function. table 2. z8 encore! xp ? 4k series package options part number adc 8-pin pdip 8-pin soic 20-pin pdip 20-pin soic 20-pin ssop 28-pin pdip 28-pin soic 28-pin ssop 8-pin qfn/ mlf-s z8f042a yes x x x x x x x x x Z8F041A no x x x x x x x x x z8f022a yes x x x x x x x x x z8f021a no x x x x x x x x x z8f012a yes x x x x x x x x x z8f011anoxxxxxxxx x
ps022815-0206 pin description z8 encore! xp ? 4k series product specification 8 the pin configurations listed are preliminary and subject to change based on manufactur- ing limitations. figure 2.z8f04xa, z8f02xa, and z8f01xa in 8-pin soic, qfn/mlf-s, or pdip package figure 3.z8f04xa, z8f02xa, and z8f01xa in 20-pin soic, ssop or pdip package figure 4.z8f04xa, z8f02xa, and z8f01xa in 28-pin soic, ssop or pdip package vss pa5/txd0/t1out /ana0/cinp/ampout pa4/rxd0/ana1/cinn/ampinn pa3/cts0 /ana2/cout/ampinp/t1in vdd pa0/t0in/t0out /xin//dbg pa1/t0out/xout/an a3/vref/clkin pa2/reset /de0/t1out 2 1 3 4 7 8 6 5 pb0/ana0/ampout pc3/cout/led pc2/ana6/led pc1/ana5/cinn/led pc0/ana4/cinp/led dbg reset /pd0 pa7/t1out pa6/t1in/t1out pb1/ana1/ampinn pb2/ana2/ampinp pb3/clkin/ana3 vdd pa0/t0in/t0out /xin pa1/t0out/xout vss pa2/de0 1 pa5/txd0 pa3/cts0 5 10 pa4/rxd0 2 3 4 6 7 8 9 20 16 11 19 18 17 15 14 13 12 pb1/ana1/ampinn pb0/ana0/ampout pc3/cout/led pc2/ana6/led pc1/ana5/cinn/led pc0/ana4/cinp/led dbg reset /pd0 pc7/led pb2/ana2/ampinp pb3/clkin/ana3 pb4/ana7 pb5/vref (pb6) avdd vdd pa0/t0in/t0out /xin pa1/t0out/xout 1 pc6/led vss 5 10 (pb7) avss pa2/de0 pa3/cts0 pa4/rxd0 14 pa5/txd0 2 3 4 6 7 8 9 11 12 13 pc5/led pc4/led pa7/t1out pa6/t1in/t1out 28 24 19 15 27 26 25 23 22 21 20 18 17 16
ps022815-0206 pin description z8 encore! xp ? 4k series product specification 9 signal descriptions table 3 describes the z8 encore! xp ? 4k series signals. refer to the section pin configu- rations on page 7 to determine the signals availabl e for the specific package styles. table 3. signal descriptions signal mnemonic i/o description general-purpose i/o ports a?d pa[7:0] i/o port a. these pins are used for general-purpose i/o. pb[7:0] i/o port b. these pins are used for general-purpose i/o. pb6 and pb7 are available only in those devices without an adc. pc[7:0] i/o port c. these pins are used for general-purpose i/o. pd[0] i/o port d. this pin is used for general-purpose output only. note: pb6 and pb7 are only available in 28-pin packag es without adc. in 28-pin packages with adc, they are replaced by av dd and av ss . uart controllers txd0 o transmit data. this signal is the tr ansmit output from the uart and irda. rxd0 i receive data. this signal is the receive input for the uart and irda. cts0 i clear to send. this signal is the flow control input for the uart. de o driver enable. this signal allows au tomatic control of external rs-485 drivers. this signal is approximat ely the inverse of the txe (transmit empty) bit in the uart status 0 register. the de signal may be used to ensure the external rs-485 driver is enabled when data is transmitted by the uart. timers t0out/t1out o timer output 0?1. these signals are outputs from the timers. t0out /t1out o timer complement output 0?1. these signals are output from the timers in pwm dual output mode. t0in/t1in i timer input 0?1. these signals are used as the capture, gating and counter inputs. comparator cinp/cinn i comparator inputs. these signals are the positive and negative inputs to the comparator. cout o comparator output.
ps022815-0206 pin description z8 encore! xp ? 4k series product specification 10 analog ana[7:0] i analog port. these signals are us ed as inputs to the analog-to-digital converter (adc). vref i/o analog-to-digital converter referenc e voltage input, or buffered output for internal reference. low-power operational amplifier (lpo) ampinp/ampinn i lpo inputs. if enabled, these pi ns drive the positive and negative amplifier inputs respectively. ampout o lpo output. if enabled, this pin is driven by the on-chip lpo. oscillators xin i external crystal input. this is the input pin to the crystal oscillator. a crystal can be connected between it and the xout pin to form the oscillator. in addition, this pin is used with external rc networks or external clock drivers to provide the system clock. xout o external crystal output. this pin is the output of the crystal oscillator. a crystal can be connected between it and the xin pin to form the oscillator. clock input clkin i clock input signal. this pin may be used to input a ttl-level signal to be used as the system clock. led drivers led o direct led drive capability. all port c pins have the cap ability to drive an led without any other external components. these pins have programmable drive strengths set by the gpio block. on-chip debugger dbg i/o debug. this signal is the control and data input and output to and from the on-chip debugger. the dbg pin is open-drain and requires an external pull-up resistor to ensure proper operation. reset reset i/o reset. generates a reset when assert ed (driven low). also serves as a reset indicator; the z8 encore! xp ? forces this pin low when in reset. this pin is open-drain and features an enabled internal pull-up resistor. power supply v dd i digital power supply. table 3. signal descriptions (continued) signal mnemonic i/o description caution:
ps022815-0206 pin description z8 encore! xp ? 4k series product specification 11 pin characteristics table 4 provides detailed informa tion about the characteristics for each pin available on the z8 encore! xp ? 4k series 20- and 28-pin devices. data in table 4 is sorted alphabeti- cally by the pin symbol mnemonic. table 5 provides detailed informa tion about the characteristics for each pin available on the z8 encore! xp ? 4k series 8-pin devices, all six i/o pins on the 8-pin packages are 5v-tolerant (unless the pull-up devices are enabled). the column in table 4 below describes 5v-tolerance fo r the 20 and 28-pin pack- ages only. av dd i analog power supply. v ss i digital ground. av ss i analog ground. note: the av dd and av ss signals are available only in 28-pin pa ckages with adc. th ey are replaced by pb6 and pb7 on 28-pin packages without adc. table 4. pin characteristics (20- and 28-pin devices) symbol mnemonic direction reset direction active low or active high tristate output internal pull- up or pull-down schmitt trigger input open drain output 5v tolerance avdd n/a n/a n/a n/a n/a n/a n/a n/a avss n/a n/a n/a n/a n/a n/a n/a na dbg i/o i n/a yes yes yes yes no pa[7:0] i/o i n/a yes programmable pull-up yes yes, programmable pa[7:2] unless pullups enabled pb[7:0] i/o i n/a yes programmable pull-up yes yes, programmable pb[7:6] unless pullups enabled pc[7:0] i/o i n/a yes programmable pull-up yes yes, programmable pc[7:3] unless pullups enabled table 3. signal descriptions (continued) signal mnemonic i/o description note:
ps022815-0206 pin description z8 encore! xp ? 4k series product specification 12 pb6 and pb7 are available only in those devices without adc. ) reset/ pd0 i/o i/o (defaults to reset ) low (in reset mode) yes (p d0 only) programmable for pd0; always on for reset yes programmable for pd0; always on for reset yes, unless pullups enabled vdd n/a n/a n/a n/a n/a n/a vss n/a n/a n/a n/a n/a n/a table 5. pin characteristics (8-pin devices) symbol mnemonic direction reset direction active low or active high tristate output internal pull- up or pull-down schmitt trigger input open drain output 5v tolerance pa0/dbg i/o i (but can change during reset if key sequence detected) n/a yes programmable pull-up yes yes, programmable yes, unless pull-ups enabled pa1 i/o i n/a yes programmable pull-up yes yes, programmable yes, unless pull-ups enabled reset / pa2 i/o i/o (defaults to reset ) low (in reset mode) yes programmable for pa2; always on for reset yes programmable for pa2; always on for reset yes, unless pull-ups enabled pa[5:3] i/o i n/a yes programmable pull-up yes yes, programmable yes, unless pull-ups enabled vdd n/a n/a n/a n/a n/a n/a n/a n/a vss n/a n/a n/a n/a n/a n/a n/a n/a table 4. pin characteristics (20- and 28-pin devices) symbol mnemonic direction reset direction active low or active high tristate output internal pull- up or pull-down schmitt trigger input open drain output 5v tolerance note:
ps022815-0206 address space z8 encore! xp ? 4k series product specification 13 address space overview the ez8 cpu can access three distinct address spaces: ? the register file contains addresses for th e general-purpose registers and the ez8 cpu, peripheral, and general-purpos e i/o port control registers. ? the program memory contains addresses fo r all memory locations having executable code and/or data. ? the data memory contains addresses for all memory locations that contain data only. these three address spaces are covered brie fly in the following subsections. for more detailed information regarding the ez8 cp u and its address space, refer to the ez8 cpu user manual available for download at www.zilog.com . register file the register file address space in the z8 encore! ? mcu is 4kb (4096 bytes). the regis- ter file is composed of two sections: control registers and general-purpose registers. when instructions are executed, registers defined as sources are read, and registers defined as destinations are written. the architecture of the ez8 cpu allows all general-purpose regis- ters to function as accumulators, address pointe rs, index registers, stack areas, or scratch pad memory. the upper 256 bytes of the 4kb register file address space are reserved for control of the ez8 cpu, the on-chip peripherals, and the i/o ports. these registers are located at addresses from f00h to fffh . some of the addresses within the 256b control register sec- tion are reserved (unavailable) . reading from a reserved register file address returns an undefined value. writing to reserved register file addresses is not recommended and can produce unpredictable results. the on-chip ram always begins at address 000h in the register file address space. the z8 encore! xp ? 4k series devices contain 256b to 1kb of on-chip ram. reading from register file addresses outside the availabl e ram addresses (and not within the control register address space) returns an undefined va lue. writing to these register file addresses produces no effect.
ps022815-0206 address space z8 encore! xp ? 4k series product specification 14 program memory the ez8 cpu supports 64kb of program me mory address space. the z8 encore! xp ? 4k series devices contain 1kb to 4kb of on-chip flash memory in the program memory address space, depending on the device. reading from program memory addresses out- side the available flash memory addresses returns ffh . writing to these unimplemented program memory addresses produces no effect. table 6 describes the program memory maps for the z8 encore! xp ? 4k series products. table 6. z8 encore! xp ? 4k series series pr ogram memory maps program memory address (hex) function z8f042a and Z8F041A products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038-0039 reserved 003a-003d oscillator fail trap vectors 003e?0fff program memory z8f022a and z8f021a products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038-0039 reserved 003a-003d oscillator fail trap vectors 003e?07ff program memory z8f012a and z8f011a products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector * see table 33 on page 51 for a list of the interrupt vectors.
ps022815-0206 address space z8 encore! xp ? 4k series product specification 15 data memory the z8 encore! xp ? 4k series does not use the ez8 cpu?s 64kb data memory address space. flash information area table 7 describes the z8 encore! xp ? 4k series flash information area. this 128b information area is accessed by setting bit 7 of the flash page select register to 1. when access is enabled, the flash information area is mapped into the program memory and overlays the 128 bytes at addresses fe00h to ff7fh . when the information area access is enabled, all reads from these program memory addresses return the information area data rather than the program memory data. access to the flash informatio n area is read-only. 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038-0039 reserved 003a-003d oscillator fail trap vectors 003e?03ff program memory table 7. z8 encore! xp ? 4k series flash memory information area map program memory address (hex) function fe00?fe3f zilog option bits/calibration data fe40?fe53 part number 20-character ascii alphanumeric code left justified and filled with ffh fe54?fe5f reserved fe60?fe7f zilog calibration data fe80?ffff reserved table 6. z8 encore! xp ? 4k series series program memory maps (continued) program memory address (hex) function * see table 33 on page 51 for a list of the interrupt vectors.
ps022815-0206 register map z8 encore! xp ? 4k series product specification 16 register map table 8 provides the address map for the re gister file of the z8 encore! xp ? 4k series devices. not all devices and pack age styles in the z8 encore! xp ? 4k series support the adc, or all of the gpio ports. consider registers for unimplemented peripherals as reserved. table 8. register file address map address (hex) register description mnemonic reset (hex) page # general purpose ram z8f042a/Z8F041A devices 000?3ff general-purpose register file ram ? xx 400?eff reserved ? xx z8f012a/z8f021a devices 000?1ff general-purpose register file ram ? xx 200?eff reserved ? xx z8f022a/z8f011a devices 000?0ff general-purpose register file ram ? xx 100?eff reserved ? xx timer 0 f00 timer 0 high byte t0h 00 76 f01 timer 0 low byte t0l 01 76 f02 timer 0 reload high byte t0rh ff 77 f03 timer 0 reload low byte t0rl ff 77 f04 timer 0 pwm high byte t0pwmh 00 77 f05 timer 0 pwm low byte t0pwml 00 78 f06 timer 0 control 0 t0ctl0 00 78 f07 timer 0 control 1 t0ctl1 00 79 timer 1 f08 timer 1 high byte t1h 00 76 f09 timer 1 low byte t1l 01 76 f0a timer 1 reload high byte t1rh ff 77 f0b timer 1 reload low byte t1rl ff 77 f0c timer 1 pwm high byte t1pwmh 00 77 f0d timer 1 pwm low byte t1pwml 00 78 xx=undefined
ps022815-0206 register map z8 encore! xp ? 4k series product specification 17 f0e timer 1 control 0 t1ctl0 00 78 f0f timer 1 control 1 t1ctl1 00 76 f10?f6f reserved ? xx uart f40 uart transmit/receive data registers txd, rxd xx 100 f41 uart status 0 register u0stat0 00 101 f42 uart control 0 register u0ctl0 00 103 f43 uart control 1 register u0ctl1 00 103 f44 uart status 1 register u0stat1 00 103 f45 uart address compare register u0addr 00 106 f46 uart baud rate high byte register u0brh ff 106 f47 uart baud rate low byte register u0brl ff 106 analog-to-digital converter (adc) f70 adc control 0 adcctl0 00 124 f71 adc control 1 adcctl1 80 124 f72 adc data high byte adcd_h xx 127 f73 adc data low bits adcd_l xx 127 f74 adc high threshold high byte adcthh ff 128 f75 reserved ? xx f76 adc low threshold high byte adctlh 00 128 f77?f7f reserved ? xx low power control f80 power control 0 pwrctl0 80 31 f81 reserved ? xx led controller f82 led drive enable leden 00 47 f83 led drive level high byte ledlvlh 00 48 f84 led drive level low byte ledlvll 00 48 f85 reserved ? xx oscillator control f86 oscillator control oscctl a0 183 f87?f8f reserved ? xx comparator 0 f90 comparator 0 control cmp0 14 131 table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page # xx=undefined
ps022815-0206 register map z8 encore! xp ? 4k series product specification 18 f91?fbf reserved ? xx interrupt controller fc0 interrupt request 0 irq0 00 55 fc1 irq0 enable high bit irq0enh 00 57 fc2 irq0 enable low bit irq0enl 00 57 fc3 interrupt request 1 irq1 00 56 fc4 irq1 enable high bit irq1enh 00 58 fc5 irq1 enable low bit irq1enl 00 59 fc6 interrupt request 2 irq2 00 56 fc7 irq2 enable high bit irq2enh 00 59 fc8 irq2 enable low bit irq2enl 00 60 fc9?fcc reserved ? xx fcd interrupt edge select irqes 00 61 fce shared interrupt select irqss 00 61 fcf interrupt control irqctl 00 61 gpio port a fd0 port a address paaddr 00 40 fd1 port a control pactl 00 42 fd2 port a input data pain xx 42 fd3 port a output data paout 00 42 gpio port b fd4 port b address pbaddr 00 40 fd5 port b control pbctl 00 42 fd6 port b input data pbin xx 42 fd7 port b output data pbout 00 42 gpio port c fd8 port c address pcaddr 00 40 fd9 port c control pcctl 00 42 fda port c input data pcin xx 42 fdb port c output data pcout 00 42 gpio port d fdc port d address pdaddr 00 40 fdd port d control pdctl 00 42 fde reserved ? xx table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page # xx=undefined
ps022815-0206 register map z8 encore! xp ? 4k series product specification 19 fdf port d output data pdout 00 42 fe0?fef reserved ? xx watch-dog timer (wdt) ff0 reset status (read-only) rststat x0 27 watch-dog timer control (write-only) wdtctl n/a 86 ff1 watch-dog timer reload upper byte wdtu 00 87 ff2 watch-dog timer reload high byte wdth 04 87 ff3 watch-dog timer reload low byte wdtl 00 88 ff4?ff5 reserved ? xx trim bit control ff6 trim bit address trmadr 00 150 ff7 trim bit data trmdr 00 151 flash memory controller ff8 flash control fctl 00 144 ff8 flash status fstat 00 145 ff9 flash page select fps 00 146 flash sector protect fprot 00 146 ffa flash programming frequency high byte ffreqh 00 147 ffb flash programming frequency low byte ffreql 00 147 ez8 cpu ffc flags ? xx refer to the ez8 cpu user manual ffd register pointer rp xx ffe stack pointer high byte sph xx fff stack pointer low byte spl xx table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page # xx=undefined
ps022815-0206 reset, stop mode recovery and low voltage detection z8 encore! xp ? 4k series product specification 20 reset, stop mode recovery and low voltage detection overview the reset controller within the z8 encore! xp ? 4k series controls reset and stop mode recovery operation and provides indication of low su pply voltage conditions. in typical operation, the following events cause a reset: ? power-on reset (por) ? voltage brown-out (vbo) ? watch-dog timer time-out (when configured by the wdt_res flash option bit to initiate a reset) ? external reset pin assertion (when the alternate reset function is enabled by the gpio register) ? on-chip debugger initiated re set (ocdctl[0] set to 1) when the device is in stop mode, a stop mo de recovery is initiated by either of the following: ? watch-dog timer time-out ? gpio port input pin transition on an enabled stop mode recovery source the low voltage detection circuitry on the device (available on the 8-pin product versions only) performs the fo llowing functions: ? generates the vbo reset when the supply voltage drops below a minimum safe level ? generates an interrupt when the supply voltage drops below a user-defined level (8-pin de- vice only) reset types the z8 encore! xp ? 4k series provides several differen t types of reset operation. stop mode recovery is considered a form of reset. table 9 lists the types of reset and their operating characteristics. the sy stem reset is longer if the external crystal oscillator is enabled by the flash option bits, allowing additional time for oscillator start-up.
ps022815-0206 reset, stop mode recovery and low voltage detection z8 encore! xp ? 4k series product specification 21 during a system reset or stop mode recovery , the internal precision oscillator requires 4 s to start up. then the z8 encore! xp ? 4k series device is held in reset for 66 cycles of the internal precision oscillator. if the crys tal oscillator is enable d in the flash option bits, this reset period is incr eased to 5000 ipo cycles. when a reset occurs because of a low voltage condition or power on reset, this delay is measured from the time that the sup- ply voltage first exceeds the por level (discusse d later in this chapter). if the external pin reset remains asserted at the end of the rese t period, the device rema ins in reset until the pin is deasserted. at the beginning of reset, all gpio pins are co nfigured as inputs with pull-up resistor dis- abled, except pd0 (or pa2 on 8-pin devices) wh ich is shared with the reset pin. on reset, the port d0 pin is configured as a bidirectional open-drain reset. the pin is internally driven low during port reset, after which the user code may reconfigure this pin as a gen- eral purpose output. during reset, the ez8 cpu and on-chip peripher als are idle; however, the on-chip crystal oscillator and watch-dog timer oscillator continue to run. upon reset, control registers w ithin the register file that have a defined reset value are loaded with their reset values. other control registers (including the stack pointer, regis- ter pointer, and flags) and general-purpo se ram are undefined following reset. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counter. prog ram execution begins at the reset vector address. because the control registers ar e re-initialized by a system reset, the system clock after reset is always the ipo. user software must reconfigure the oscillator control block, such that the correct system clock source is enabled and selected. table 9. reset and stop mode recovery characteristics and latency reset type reset characteristics and latency control registers ez8 cpu reset latency (delay) system reset reset (as app licable) reset 66 in ternal precision oscillator cycles system reset with crystal oscillator enabled reset (as applicable) res et 5000 internal precision oscillator cycles stop mode recovery un affected, except wdt_ctl and osc_ctl registers reset 66 internal precision oscillator cycles + ipo startup time stop mode recovery with crystal oscillator enabled unaffected, except wdt_ctl and osc_ctl registers reset 5000 internal prec ision oscillator cycles
ps022815-0206 reset, stop mode recovery and low voltage detection z8 encore! xp ? 4k series product specification 22 reset sources table 10 lists the possible sources of a system reset. power-on reset z8 encore! xp ? 4k series devices contain an internal power-on reset (por) circuit. the por circuit monitors the supply voltage and holds the device in the reset state until the supply voltage reaches a safe operating level. after the supply voltage exceeds the por voltage threshold (v por ), the device is held in the r eset state until the por counter has timed out. if the crystal oscillator is enable d by the option bits, this timeout is longer. after the z8 encore! xp ? 4k series device exits the power-on reset state, the ez8 cpu fetches the reset vector. following power-on reset, the por status bit in the watch-dog timer control (wdtctl) register is set to 1. figure 5 illustrates power-on reset operation. refer to the electrical characteristics on page 212 for the por threshold voltage (v por ). table 10. reset sources and resulting reset type operating mode reset source special conditions normal or halt modes power-on reset / voltage brown- out reset delay begins after supply voltage exceeds por level watch-dog timer time-out when configured for reset none reset pin assertion all reset pulses less than three system clocks in width are ignored. on-chip debugger initiated reset (ocdctl[0] set to 1) system reset, except the on-chip debugger is unaffected by the reset stop mode power-on reset / voltage brown- out reset delay begins after supply voltage exceeds por level reset pin assertion all reset pulses less than the specified analog delay are ignored. see table 134 on page 219 dbg pin driven low none
ps022815-0206 reset, stop mode recovery and low voltage detection z8 encore! xp ? 4k series product specification 23 figure 5.power-on reset operation voltage brown-out reset the devices in the z8 encore! xp ? 4k series provide low voltage brown-out (vbo) pro- tection. the vbo circuit senses when the supply voltage drops to an unsafe level (below the vbo threshold voltage) and forces the device into the reset state. while the supply voltage remains below the power- on reset voltage threshold (v por ), the vbo block holds the device in the reset. after the supply voltage again exceeds the po wer-on reset voltage threshold, the device progresses through a full system reset sequenc e, as described in the power-on reset sec- tion. following power-on reset, the por stat us bit in the reset status (rststat) regis- ter is set to 1. figure 6 illustrates voltage brown-out op eration. refer to the chapter electrical characteristics on page 212 for the vbo and por threshold voltages (v vbo and v por ). the voltage brown-out circuit can be either enabled or disabled during stop mode. operation during stop mode is set by the vbo_ao flash option bit. refer to the flash option bits chapter for info rmation about configuring vbo_ao . vcc = 0.0v vcc = 3.3v v por v vbo internal precision internal reset signal program execution oscillator start-up por counter delay optional xtal counter delay oscillator crystal oscillator note: not to scale
ps022815-0206 reset, stop mode recovery and low voltage detection z8 encore! xp ? 4k series product specification 24 figure 6.voltage brown-out reset operation the por level is greater than the vbo leve l by the specified hysteresis value. this ensures that the device undergoes a power-on reset after recovering from a vbo condi- tion. watch-dog timer reset if the device is in normal or stop mode, the watch-dog timer can initiate a system reset at time-out if the wdt_res flash optio n bit is programmed to 1. this is the unprogrammed state of the wdt_res flash option bit. if the bit is programmed to 0, it configures the watch-dog timer to cause an in terrupt, not a system reset, at time-out. the wdt bit in the reset status (rststat) regi ster is set to signify that the reset was initiated by the watch-dog timer. external reset input the reset pin has a schmitt-triggered input and an internal pull-up resistor. once the reset pin is asserted for a minimum of four sy stem clock cycles, th e device progresses through the system reset sequen ce. because of the possible asynchronicity of the system clock and reset signals, the required reset duration may be as short as three clock periods vcc = 3.3v v por v vbo internal reset signal program execution program execution voltage brownout vcc = 3.3v system clock por counter delay note: not to scale
ps022815-0206 reset, stop mode recovery and low voltage detection z8 encore! xp ? 4k series product specification 25 and as long as four. a reset pulse three cloc k cycles in duration might trigger a reset; a pulse four cycles in duration always triggers a reset. while the reset input pin is asserted low, the z8 encore! xp ? 4k series devices remain in the reset state. if the reset pin is held low beyond the system reset time- out, the device exits the reset state on th e system clock rising edge following reset pin deassertion. following a system re set initiated by the external reset pin, the ext sta- tus bit in the reset status (rststat) register is set to 1. external reset indicator during system reset or when enabled by the gpio logic (see see port a?d control reg- isters on page 42. ), the reset pin functions as an open-drain (active low) reset mode indicator in addition to the input functionality . this reset output feature allows an z8 encore! xp ? 4k series device to reset other compon ents to which it is connected, even if that reset is caused by internal sour ces such as por, vbo or wdt events. after an internal reset even t occurs, the internal circu itry begins driving the reset pin low. the reset pin is held low by the internal circuitry until the appropriate delay listed in table 9 has elapsed. on-chip debugger initiated reset a power-on reset can be initiated usi ng the on-chip debugger by setting the rst bit in the ocd control register. the on-chip debugger block is not reset but the rest of the chip goes through a normal system reset. the rst bit automatically clears during the system reset. following th e system reset the por bit in the wdt control register is set. stop mode recovery stop mode is entered by execution of a stop instruction by the ez8 cpu. refer to the chapter low-power modes on page 29 for detailed stop mode information. during stop mode recovery, the cpu is held in reset for 66 ipo cycles if the crystal oscillator is disabled or 5000 cycles if it is enabled. the smr delay (see table 134 on page 219 ) t smr , also includes the time requ ired to start up the ipo. stop mode recovery does not affect onchip registers other than the watchdog timer control register (wdtctl) and the oscilla tor control register (oscctl). after any stop mode recovery, the ipo is enabled and selected as the system clock. if another sys- tem clock source is required, the stop mode recovery code must reconfigure the oscilla- tor control block such that the correct sy stem clock source is enabled and selected. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counte r. program execution begins at the reset vec- tor address. following stop mode recove ry, the stop bit in the reset status
ps022815-0206 reset, stop mode recovery and low voltage detection z8 encore! xp ? 4k series product specification 26 (rststat) register is set to 1. table 11 lists the stop mode recovery sources and resulting actions. the text following provides more detailed information about each of the stop mode recovery sources. stop mode recovery using watch-dog timer time-out if the watch-dog timer times out during stop mode, the device undergoes a stop mode recovery sequence. in the reset stat us (rststat) register, the wdt and stop bits are set to 1. if the watch- dog timer is configured to ge nerate an interrupt upon time- out and the z8 encore! xp ? 4k series device is configured to respond to interrupts, the ez8 cpu services the watch-do g timer interrupt request fo llowing the normal stop mode recovery sequence. stop mode recovery using a gpio port pin transition each of the gpio port pins may be configured as a stop mode recovery input source. on any gpio pin enabled as a stop mode re covery source, a change in the input pin value (from high to low or from low to high ) initiates stop mode recovery. note that smr pulses shorter than specified will not trigger a recovery. (see table 134 on page 219 ). when this happens, the stop bit in the reset status (rststat) register is set to 1. in stop mode, the gpio port input data registers (p x in) are disabled. the port input data registers record the port transition only if the signal stays on the port pin through the end of the stop mode recovery delay. as a result, short pulses on the port pin can initiate stop mode recovery without being written to the port input data register or without initiating an interrupt (if enabled for that pin). table 11. stop mode recovery sources and resulting action operating mode stop mode recovery source action stop mode watch-dog timer time-out when configured for reset stop mode recovery watch-dog timer time-out when configured for interrupt stop mode recovery followed by interrupt (if interrupts are enabled) data transition on any gpio port pin enabled as a stop mode recovery source stop mode recovery assertion of external reset pin system reset debug pin driven low system reset caution:
ps022815-0206 reset, stop mode recovery and low voltage detection z8 encore! xp ? 4k series product specification 27 stop mode recovery usi ng the external reset pin when the z8 encore! xp ? 4k series device is in st op mode and the external reset pin is driven low, a system re set occurs. because of a glitch filter operating on the reset pin, the low pulse must be greater than the mi nimum width specified, or it is ignored. see electrical characteristics on page 212 for details. low voltage detection in addition to the voltage brown-out reset (v bo) described above, it is also possible to generate an interrupt when the supply voltage drops be low a user-selected value. see trim bit address 0003h on page 154. for details about the low voltage detection (lvd) threshold levels available. the lvd function is available on the 8-pin product versions only. when the supply voltage drops below the lvd threshold, the lvd bit of the reset status (rststat) register is set to one. this bit remains one until the low-voltage condition goes away. reading or writing this bit does not clear it. the lvd circuit can also generate an interrupt when so enabled. ( see interrupt vectors and priority on page 53. ) the lvd bit is not latched, so enabling the interrupt is the only way to guarantee detection of a tran- sient low voltage event. the lvd functionality de pends on circuitry shared with the vbo block; therefore dis- abling the vbo also disables the lvd. reset register definitions reset status register the reset status (rststat) register is a read-o nly register that indicates the source of the most recent reset event, indicates a st op mode recovery ev ent, and indicates a watch-dog timer time-out. reading this re gister resets the upper four bits to 0. this register shares its address with the watch-dog timer control register, which is write- only ( table 12 ).
ps022815-0206 reset, stop mode recovery and low voltage detection z8 encore! xp ? 4k series product specification 28 por?power-on reset indicator if this bit is set to 1, a power-on reset event occurred. this bit is reset to 0 if a wdt time- out or stop mode recovery occurs. this bit is also reset to 0 when the register is read. stop?stop mode recovery indicator if this bit is set to 1, a stop mode recovery occurred. if the stop and wdt bits are both set to 1, the stop mode recovery oc curred because of a wdt time-out. if the stop bit is 1 and the wdt bit is 0, the stop mode recovery was not caused by a wdt time-out. this bit is reset by a power-on reset or a wdt time-out that occurred while not in stop mode. reading this register also resets this bit. wdt?watch-dog timer time-out indicator if this bit is set to 1, a wdt time-out occurred. a power-on reset resets this pin. a stop mode recovery from a change in an input pin also resets this bit. reading this register resets this bit. this read must o ccur before clearing the wdt interrupt. ext?external reset indicator if this bit is set to 1, a reset initiated by the external reset pin occurred. a power-on reset or a stop mode recovery from a change in an input pin resets this bit. reading this register resets this bit. reserved?must be 0. lvd?low voltage detection indicator if this bit is set to 1 the current state of th e supply voltage is belo w the low voltage detec- tion threshold. this value is no t latched but is a real-time in dicator of the supply voltage level. table 12. reset status register (rststat) bits 7 6 5 4 3 2 1 0 field por stop wdt ext reserved lvd reset see descriptions below 0 0 0 0 0 r/w rrrrrrrr addr ff0h reset or stop mode recovery event por stop wdt ext power-on reset 1000 reset using reset pin assertion 0001 reset using watch-dog timer time-out 0010 reset using the on-chip debugger (octctl[1] set to 1) 1000 reset from stop mode using dbg pin driven low 1000 stop mode recovery using gpio pin transition 0100 stop mode recovery using watch-dog timer time-out 0110
ps022815-0206 low-power modes z8 encore! xp ? 4k series product specification 29 low-power modes overview the z8 encore! xp ? 4k series products contain power-saving features. the highest level of power reduction is provided by the stop mode. the next lower level of power reduc- tion is provided by the halt mode. further power savings can be implemented by disabling individual peripheral blocks while in active mode (defined as be ing in neither stop nor halt mode). stop mode executing the ez8 cpu?s stop instruction pl aces the device into stop mode. in stop mode, the operating characteristics are: ? primary crystal oscillator and in ternal precision oscillator are stopped; xin and xout (if previously enabled) are disabled, and pa0/pa 1 revert to the states programmed by the gpio registers. ? system clock is stopped. ? ez8 cpu is stopped. ? program counter (pc) stops incrementing. ? watch-dog timer?s internal rc oscillator conti nues to operate if enabled by the oscillator control register. ? if enabled, the watch-dog timer logic continues to operate. ? if enabled for operation in stop mode by the associated flash option bit, the voltage- brown out protection circuit continues to operate. ? low-power operational amplifier continues to operate if enabled by the power control register to do so. ? all other on-chip peripherals are idle. to minimize current in stop mode, all gpio pins that are configured as digital inputs must be driven to one of the supply rails (v cc or gnd). additionally, any gpios config- ured as outputs should also be driven to one of the supply rails. the device can be brought out of stop mode using stop mode recovery. for more information about stop mode recovery refer to reset, stop mode recovery and low voltage detection on page 20 .
ps022815-0206 low-power modes z8 encore! xp ? 4k series product specification 30 halt mode executing the ez8 cpu?s halt instruction pl aces the device into halt mode. in halt mode, the operating characteristics are: ? primary oscillator is enable d and continues to operate. ? system clock is enabled and continues to operate. ? ez8 cpu is stopped. ? program counter (pc) stops incrementing. ? watch-dog timer?s internal rc oscillator continues to operate. ? if enabled, the watch-dog timer continues to operate. ? all other on-chip peripherals c ontinue to operate, if enabled. the ez8 cpu can be brought out of halt mode by any of the following operations: ? interrupt ? watch-dog timer time-out (interrupt or reset) ? power-on reset ? voltage-brown out reset ? external reset pin assertion to minimize current in halt mode, all gpio pins that are configured as inputs must be driven to one of the supply rails (v cc or gnd). peripheral-level power control in addition to the stop and ha lt modes, it is possible to disable each peripheral on each of the z8 encore! xp ? 4k series devices. disabling a given peripheral minimizes its power consumption. power control register definitions power control register 0 each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the block. the default state of the low-power operationa l amplifier (lpo) is off. to use the lpo, clear the lpo bit, turning it on. clearing this bit might interfere with normal adc mea-
ps022815-0206 low-power modes z8 encore! xp ? 4k series product specification 31 surements on ana0 (the lpo output). this b it enables the amplifier even in stop mode. if the amplifier is not required in stop mode, disable it. failure to pe rform this results in stop mode currents greater than specified. this register is only reset du ring a power-on reset sequence. other system reset events do not affect it. lpo ? low-power operational amplifier disable 0 = lpo is enabled (this ap plies even in stop mode). 1 = lpo is disabled. reserved?must be 0. vbo?voltage brown-out detector disable this bit and the vbo_ao flas h option bit must both enable the vbo for the vbo to be active. 0 = vbo enabled 1 = vbo disabled temp?temperature sensor disable 0 = temperature sensor enabled 1 = temperature sensor disabled adc?analog-to-digital converter disable 0 = analog-to-digital converter enabled 1 = analog-to-digital converter disabled comp?comparator disable 0 = comparator is enabled 1 = comparator is disabled reserved?must be 0. asserting any power control bit will disable th e targeted block, rega rdless of any enable bits contained in the target block?s control registers. table 13. power control register 0 (pwrctl0) bits 7 6 5 4 3 2 1 0 field lpo reserved vbo temp adc comp reserved reset 10000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f80h note: note:
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 32 general-purpose i/o overview the z8 encore! xp ? 4k series products support a maximum of 25 port pins (ports a?d) for general-purpose input/output (gpio) opera tions. each port contains control and data registers. the gpio control registers determin e data direction, open-drain, output drive current, programmable pull-ups, stop mode recovery functionality, and alternate pin functions. each port pin is individually prog rammable. in addition, the port c pins are capable of direct led drive at programmable drive strengths. gpio port availability by device table 14 lists the port pins available w ith each device and package type. table 14. port availability by device and package type devices package 10-bit adc port a port b port c port d total i/o z8f042asb, z8f042apb, z8f042aqb z8f022asb, z8f022apb, z8f022aqb z8f012asb, z8f012apb, z8f012aqb 8-pin yes [5:0] no no no 6 Z8F041Asb, Z8F041Apb, Z8F041Aqb z8f021asb, z8f021apb, z8f021aqb z8f011asb, z8f011apb, z8f011aqb 8-pin no [5:0] no no no 6 z8f042aph, z8f042ahh, z8f042ash z8f022aph, z8f022ahh, z8f022ash z8f012aph, z8f012ahh, z8f012ash 20-pin yes [7:0] [3:0] [3:0] [0] 17 Z8F041Aph, Z8F041Ahh, Z8F041Ash z8f021aph, z8f021ahh, z8f021ash z8f011aph, z8f011ahh, z8f011ash 20-pin no [7:0] [3:0] [3:0] [0] 17 z8f042apj, z8f042asj, z8f042ahj z8f022apj, z8f022asj, z8f022ahj z8f012apj, z8f012asj, z8f012ahj 28-pin yes [7:0] [5:0] [7:0] [0] 23 Z8F041Apj, Z8F041Asj, Z8F041Ahj z8f021apj, z8f021asj, z8f021ahj z8f011apj, z8f011asj, z8f011ahj 28-pin no [7:0] [7:0] [7:0] [0] 25
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 33 architecture figure 7 illustrates a simplified block diagram of a gpio port pin. in this figure, the abil- ity to accommodate alternate functions and variab le port current drive strength is not illus- trated. figure 7.gpio port pin block diagram gpio alternate functions many of the gpio port pins can be used for general-purpose i/o and access to on-chip peripheral functions such as the timers and serial communication de vices. the port a?d alternate function sub-registers configure the se pins for either general-purpose i/o or alternate function operation. when a pin is conf igured for alternate fu nction, control of the port pin direction (input/output) is passed from the port a?d data direction registers to the alternate function ass igned to this pin. table 15 on page 36 lists the alternate functions possible with each port pin. for those pins w ith more one alternate function, the alternate function is defined through alternate function sets sub-registers afs1 and afs2. the crystal oscillator fu nctionality is not controlled by th e gpio block. when the crystal oscillator is enabled in the os cillator control block, the gpio functionality of pa0 and pa1 is overridden. in that case, th ose pins function as input and output for the crystal oscillator. d q dq d q gnd vdd port output control port data direction port output data register port input data register port pin data bus system clock system clock schmitt trigger
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 34 pa0 and pa6 contain two different timer fu nctions, a timer input and a complementary timer output. both of these fu nctions require the same gpio configuration, the selection between the two is based on the timer mode. see timers on page 62 for more details. direct led drive the port c pins provide a current sinked output capable of driving an led without requir- ing an external resistor. the output sinks cu rrent at programmable levels of 3 ma, 7 ma, 13 ma and 20 ma. this mode is enabled th rough the alternate function sub-register afs1 and is programmable through the led control registers. the led drive enable (leden) register turns on the drivers. the led drive level (ledlvlh and ledlvll) registers select the sink current. for correct function, the led anode must be connected to v dd and the cathode to the gpio pin. using all port c pins in led drive mode w ith maximum current may result in excessive total current. refer to the electrical characteristics on page 212 for the maximum total current for the applicable package. shared reset pin on the 20 and 28-pin devices, the port d0 pin shares functio n with a bi-directional reset pin. unlike all other i/o pins, this pin does not default to gpio function on power-up. this pin acts as a bi-directiona l reset until user software re-c onfigures it. the port d0 pin is output-only when in gpio mode. on the 8-pin product versions, the reset pin is shared with porta2, but the pin is not lim- ited to output-only when in gpio mode. if pa2 on the 8-pin product is reconfigured as an input, take care that no external stim- ulus drives the pin low during any reset sequence. since pa2 returns to its reset al- ternate function during system resets, driving it low will hold the chip in a reset state until the pin is released. the same applies to the pdo pin on the 28-pin product. shared debug pin on the 8-pin version of this device only, th e debug pin shares function with the porta0 gpio pin. this pin performs as a general purpose input pin on power-up, but the debug logic monitors this pin during the reset sequence to determine if the unlock sequence occurs. if the unlock sequence is present, the debug function is unlocked and the pin no longer functions as a gpio pin. if it is not present, the debug feature is disabled until/ unless another reset event occurs. for more details, see on-chip debugger on page 167 caution:
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 35 crystal oscillator override for systems using a crystal oscillator, pa0 and pa1 are used to connect the crystal. when the crystal oscillator is enabled (see oscillator control register definitions on page 183 ), the gpio settings are overridden and pa0 and pa1 are disabled. 5v tolerance all six i/o pins on the 8-pin devices are 5v-tolerant, unless the programmable pull-ups are enabled. if the pull- ups are enabled and in puts higher than v dd are applied to these parts, excessive current flows through those pu ll-up devices and can damage the chip. in the 20- and 28-pin versions of this devi ce, any pin which shares functionality with an adc, crystal or comparator port is not 5v-tolerant, including pa[1:0], pb[5:0] and pc[2:0]. all other signal pins are 5v-toler ant, and can safely handle inputs higher than v dd except when the programm able pull-ups are enabled. external clock setup for systems using an external ttl drive, pb 3 is the clock source for 20- and 28-pin devices. in this case, configure pb3 for a lternate function clkin. write the oscillator control (oscctl)register (page 1 83) such that the external o scillator is selected as the system clock. for 8-pin devi ces use pa1 instead of pb3. note:
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 36 table 15. port alternate function mapping (non 8-pin parts) port pin mnemonic alternate function description alternate function set register afs1 port a pa0 t0in/t0out * timer 0 input/timer 0 output complement n/a reserved pa1 t0out timer 0 output reserved pa2 de0 uart 0 driver enable reserved pa3 cts0 uart 0 clear to send reserved pa4 rxd0/irrx0 uart 0 / irda 0 receive data reserved pa5 txd0/irtx0 uart 0 / irda 0 transmit data reserved pa6 t1in/t1out * timer 1 input/timer 1 output complement reserved pa7 t1out timer 1 output reserved note: because there is only a single alternate function for each port a pin, the alternate function set registers are not implemented for port a. enabling alternate function selections as described in port a?d alternate function sub-registers on page 42 automatically enables the associated alternate function. * whether pa0/pa6 take on the timer input or timer output complement function depends on the timer configuration as described in timer pin signal operation on page 75 .
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 37 port b pb0 reserved afs1[0]: 0 ana0/ampout adc analog in put/lpo output afs1[0]: 1 pb1 reserved afs1[1]: 0 ana1/ampinn adc analog input/lpo input (n) afs1[1]: 1 pb2 reserved afs1[2]: 0 ana2/ampinp adc analog input/lpo input (p) afs1[2]: 1 pb3 clkin external clock input afs1[3]: 0 ana3 adc analog input afs1[3]: 1 pb4 reserved afs1[4]: 0 ana7 adc analog input afs1[4]: 1 pb5 reserved afs1[5]: 0 vref* adc voltage reference afs1[5]: 1 pb6 reserved afs1[6]: 0 reserved afs1[6]: 1 pb7 reserved afs1[7]: 0 reserved afs1[7]: 1 note: because there are at most two choices of altern ate function for any pin of port b, the alternate function set register afs2 is not used to select the function. also, altern ate function selection as described in port a?d alternate function sub-registers on page 42 must also be enabled. * vref is available on pb5 in 28-pin products only. table 15. port alternate function ma pping (continued)(non 8-pin parts) port pin mnemonic alternate function description alternate function set register afs1
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 38 port c pc0 reserved afs1[0]: 0 ana4/cinp/led drive adc or comparator input, or led drive afs1[0]: 1 pc1 reserved afs1[1]: 0 ana5/cinn/ led drive adc or comparator input, or led drive afs1[1]: 1 pc2 reserved afs1[2]: 0 ana6/led/ vref* adc analog input, led drive, or adc voltage reference afs1[2]: 1 pc3 cout comparator output afs1[3]: 0 led led drive afs1[3]: 1 pc4 reserved afs1[4]: 0 led led drive afs1[4]: 1 pc5 reserved afs1[5]: 0 led led drive afs1[5]: 1 pc6 reserved afs1[6]: 0 led led drive afs1[6]: 1 pc7 reserved afs1[7]: 0 led led drive afs1[7]: 1 note: because there are at most two choices of altern ate function for any pin of port c, the alternate function set register afs2 is not used to select the function. also, altern ate function selection as described in port a?d alternate function sub-registers on page 42 must also be enabled. * vref is available on pc2 in 20-pin products only. table 15. port alternate function ma pping (continued)(non 8-pin parts) port pin mnemonic alternate function description alternate function set register afs1
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 39 table 16. port alternate function mapping (8-pin parts) port pin mnemonic alternate function description alternate function select register afs1 alternate function select register afs2 port a pa0 t0in timer 0 input afs1[0]: 0 afs1[0]: 0 reserved afs1[0]: 0 afs2[0]: 1 reserved afs1[0]: 1 afs2[0]: 0 t0out timer 0 output complement afs1[0]: 1 afs2[0]: 1 pa1 t0out timer 0 output afs1[1]: 0 afs2[1]: 0 reserved afs1[1]: 0 afs2[1]: 1 clkin external clock input afs1[1]: 1 afs2[1]: 0 analog functions* adc analog in put/vref afs1[1]: 1 afs2[1]: 1 pa2 de0 uart 0 driver e nable afs1[2]: 0 afs2[2]: 0 reset external reset afs1[2]: 0 afs2[2]: 1 t1out timer 1 output afs1[2]: 1 afs2[2]: 0 reserved afs1[2]: 1 afs2[2]: 1 pa3 cts0 uart 0 clear to send afs1[3]: 0 afs2[3]: 0 cout comparator output afs1[3]: 0 afs2[3]: 1 t1in timer 1 input afs1[3]: 1 afs2[3]: 0 analog functions* adc analog input/lpo input (p) afs1[3]: 1 afs2[3]: 1 pa4 rxd0 uart 0 receive da ta afs1[4]: 0 afs2[4]: 0 reserved afs1[4]: 0 afs2[4]: 1 reserved afs1[4]: 1 afs2[4]: 0 analog functions* adc/co mparator input (n)/lpo input (n) afs1[4]: 1 afs2[4]: 1 pa5 txd0 uart 0 transmit data afs1[5]: 0 afs2[5]: 0 t1out timer 1 output complement afs1[5]: 0 afs2[5]: 1 * analog functions include adc inputs, adc reference, comparator inputs and lpo ports. note: also, alternate function selection as described in port a?d alternate function sub-registers on page 42 must be enabled.
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 40 gpio interrupts many of the gpio port pins can be used as interrupt sources. some port pins can be con- figured to generate an interrupt request on eith er the rising edge or falling edge of the pin input signal. other port pin interrupt sources generate an interrupt when any edge occurs (both rising and falling). refer to the chapter interrupt controller on page 50 for more information about interrupts using the gpio pins. gpio control register definitions four registers for each port provide access to gpio control, input data, and output data. table 17 lists these port registers. use the port a?d address and control registers together to provide access to sub-regist ers for port configuration and control. port a (cont) reserved afs2[5]: 1 afs1[5]: 0 analog functions* adc/co mparator input (p) lpo output afs2[5]: 1 afs1[5]: 1 table 17. gpio port registers and sub-registers port register mnemon ic port register name p x addr port a?d address register (selects sub-registers) p x ctl port a?d control register (provides access to sub-registers) p x in port a?d input data register p x out port a?d output data register port sub-register mnem onic port register name p x dd data direction p x af alternate function table 16. port alternate function mapping (8-pin parts) (continued) port pin mnemonic alternate function description alternate function select register afs1 alternate function select register afs2 * analog functions include adc inputs, adc reference, comparator inputs and lpo ports. note: also, alternate function selection as described in port a?d alternate function sub-registers on page 42 must be enabled.
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 41 port a?d address registers the port a?d address registers select the gp io port functionality accessible through the port a?d control registers. the port a?d address and control registers combine to pro- vide access to all gpio port controls ( table 18 ). paddr[7:0]?port address the port address selects one of the sub-regi sters accessible through the port control reg- ister. p x oc output control (open-drain) p x hde high drive enable p x smre stop mode recove ry source enable p x pue pull-up enable pxafs1 alternate function set 1 pxafs2 alternate function set 2 table 18. port a?d gpio address registers (p x addr) bits 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fd0h, fd4h, fd8h, fdch paddr[7:0] port control sub-register accessi ble using the port a?d control registers 00h no function. provides some protection against accidental port reconfiguration. 01h data direction 02h alternate function 03h output control (open-drain) 04h high drive enable 05h stop mode recovery source enable. 06h pull-up enable 07h alternate function set 1 08h alternate function set 2 09h?ffh no function table 17. gpio port registers and sub-registers (continued) port register mnemon ic port register name
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 42 port a?d control registers the port a?d control registers set the gpio port operation. the value in the correspond- ing port a?d address register determines which sub-register is read from or written to by a port a?d control register transaction ( table 19 ). pctl[7:0]?port control the port control register provides access to a ll sub-registers that configure the gpio port operation. port a?d data direction sub-registers the port a?d data direction sub-register is accessed through the port a?d control regis- ter by writing 01h to the port a?d address register ( table 20 ). dd[7:0]?data direction these bits control the direction of the associa ted port pin. port alternate function opera- tion overrides the data direction register setting. 0 = output. data in the port a?d output da ta register is driven onto the port pin. 1 = input. the port pin is sampled and the va lue written into the port a?d input data reg- ister. the output driver is tristated. port a?d alternate fu nction sub-registers the port a?d alternate fu nction sub-register ( table 21 ) is accessed through the port a? d control register by writing 02h to the port a?d address register. the port a?d alter- nate function sub-registers enable the alternat e function selection on pins. if disabled, pins table 19. port a?d control registers (p x ctl) bits 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fd1h, fd5h, fd9h, fddh table 20. port a?d data direction sub-registers (pxdd) bits 7 6 5 4 3 2 1 0 field dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 01h in port a?d address register, access ible through the port a?d control register
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 43 functions as gpio. if enabled, select one of four alternate functions using alternate func- tion set subregisters 1 and 2 as described in the port a?d alternate function set 1 sub- registers on page 45 and port a?d alternate function set 2 sub-registers on page 46 . refer to the gpio alternate functions on page 33 to determine the alternate function asso- ciated with each port pin. do not enable alternate functions for gpio port pins for which there is no associated alternate function. failure to follow this guideline can result in unpredictable operation. af[7:0]?port alternate function enabled 0 = the port pin is in normal mode and the ddx bit in the port a?d data direction sub- register determines the direction of the pin. 1 = the alternate function se lected through alternate fu nction set sub-registers is enabled. port pin operation is co ntrolled by the alternate function. port a?d output control sub-registers the port a?d output control sub-register ( table 22 ) is accessed through the port a?d control register by writing 03h to the port a?d address regi ster. setting the bits in the port a?d output control sub-registers to 1 configures the specified port pins for open- drain operation. these sub-registers affect the pi ns directly and, as a result, alternate func- tions are also affected. poc[7:0]?port output control these bits function independently of the a lternate function bit and always disable the table 21. port a?d alternate function sub-registers (pxaf) bits 7 6 5 4 3 2 1 0 field af7 af6 af5 af4 af3 af2 af1 af0 reset 00h (ports a?c); 01h (port d); 04h (port a of 8-pin device) r/w r/w addr if 02h in port a?d address register, access ible through the port a?d control register table 22. port a?d output control sub-registers (pxoc) bits 7 6 5 4 3 2 1 0 field poc7 poc6 poc5 poc4 poc3 poc2 poc1 poc0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 03h in port a?d address register, access ible through the port a?d control register caution:
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 44 drains if set to 1. 0 = the source current is enabled for any outp ut mode (unless overridden by the alternate function). (push-pull output) 1 = the source current for the associated pin is disabled (open-drain mode). port a?d high drive enable sub-registers the port a?d high drive enable sub-register ( table 23 ) is accessed through the port a?d control register by writing 04h to the port a?d address register. setting the bits in the port a?d high drive enable sub-registers to 1 configures the spec ified port pins for high current output drive operation. the port a?d high drive enable sub-register affects the pins directly and, as a result, a lternate functions are also affected. phde[7:0]?port high drive enabled 0 = the port pin is configured fo r standard output current drive. 1 = the port pin is configured for high output current drive. port a?d stop mode recovery source enable sub-registers the port a?d stop mode recovery source enable sub-register ( table 24 ) is accessed through the port a?d cont rol register by writing 05h to the port a?d address register. setting the bits in the port a?d stop mode recovery source enable sub-registers to 1 configures the specified port pins as a stop mode recovery source. during stop mode, any logic transition on a port pin enabled as a stop mode recovery source initiates stop mode recovery. psmre[7:0]?port stop mode recovery source enabled 0 = the port pin is not configured as a stop mode recovery source. transitions on this table 23. port a?d high drive enable sub-registers (pxhde) bits 7 6 5 4 3 2 1 0 field phde7 phde6 phde5 phde4 phde3 phde2 phde1 phde0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 04h in port a?d address register, access ible through the port a?d control register table 24. port a?d stop mode recovery source enable sub-registers (pxsmre) bits 7 6 5 4 3 2 1 0 field psmre7 psmre6 psmre5 psmre4 psmre3 psmre2 psmre1 psmre0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 05h in port a?d address register, access ible through the port a?d control register
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 45 pin during stop mode do not initiate stop mode recovery. 1 = the port pin is configured as a stop mo de recovery source. any logic transition on this pin during stop mode initiates stop mode recovery. port a?d pull-up enable sub-registers the port a?d pull-up enable sub-register ( table 25 ) is accessed through the port a?d control register by writing 06h to the port a?d address regi ster. setting the bits in the port a?d pull-up enable sub-registers enable s a weak internal resi stive pull-up on the specified port pins. ppue[7:0]?port pull-up enabled 0 = the weak pull-up on the port pin is disabled. 1 = the weak pull-up on the port pin is enabled. port a?d alternate function set 1 sub-registers the port a?d alternate func tion set1 sub-register ( table 26 ) is accessed through the port a?d control register by writing 07h to the port a?d addres s register. the alternate function set 1 sub-registers selects the alternat e function available at a port pin. alternate functions selected by setting or clearing bits of this register are defined in gpio alternate functions on page 33 . alternate function selection on port pins must also be enabled as decribed in port a?d alternate function sub-registers on page 42 . pafs1[7:0]?port alternate function set 1 0 = port alternate function selected as defined in tables 15 and 16 in the gpio alternate table 25. port a?d pull-up enable sub-registers (pxpue) bits 7 6 5 4 3 2 1 0 field ppue7 ppue6 ppue5 ppue4 ppue3 ppue2 ppue1 ppue0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 06h in port a ? d address register, accessible through the port a ? d control register table 26. port a?d alternate function set 1 sub-registers (pxafs1) bits 7 6 5 4 3 2 1 0 field pafs17 pafs16 pafs15 pafs14 pafs13 pafs12 pafs11 pafs10 reset 00h (all ports of 20/28 pin devices); 04h (port a of 8-pin device) r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 07h in port a?d address register, access ible through the port a?d control register note:
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 46 functions section. 1 = port alternate function selected as defined in tables 15 and 16 in the gpio alternate functions section. port a?d alternate function set 2 sub-registers the port a?d alternate func tion set 2 sub-register ( table 27 ) is accessed through the port a?d control register by writing 08h to the port a?d address register. the alternate function set 2 sub-registers selects the alternat e function available at a port pin. alternate functions selected by setting or clearing bits of this register is defined in table 16 in the section gpio alternate functions on page 33 . alternate function selection on port pins must also be enabled as decribed in port a?d alternate function sub-registers on page 42 . pafs2[7:0]?port alternate function set 2 0 = port alternate function selected as defined in table 16 gpio alternate functions sec- tion. 1 = port alternate function selected as defined in table 16 gpio alternate functions sec- tion. port a?c input data registers reading from the port a?c input data registers ( table 28 ) returns the sampled values from the corresponding port pi ns. the port a?c input data registers are read-only. the value returned for any unused ports is 0. unused ports include those missing on the 8- and 28-pin packages, as well as those missing on the adc-enabled 28-pin packages. table 27. port a?d alternate function set 2 sub-registers (pxafs2) bits 7 6 5 4 3 2 1 0 field pafs27 pafs26 pafs25 pafs24 pafs23 pafs22 pafs21 pafs20 reset 00h (all ports of 20/28 pin devices); 04h (port a of 8-pin device) r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 08h in port a?d address register, access ible through the port a?d control register table 28. port a?c input data registers (pxin) bits 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset xxxxxxxx r/w rrrrrrrr addr fd2h, fd6h, fdah note:
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 47 pin[7:0]?port input data sampled data from the corresponding port pin input. 0 = input data is logical 0 (low). 1 = input data is logical 1 (high). port a?d output data register the port a?d output data register ( table 29 ) controls the output data to the pins. pout[7:0]?port output data these bits contain the data to be driven to th e port pins. the values are only driven if the corresponding pin is configured as an output and the pin is not configured for alternate function operation. 0 = drive a logical 0 (low). 1= drive a logical 1 (high). high value is not driven if the drain has been disabled by set- ting the corresponding port outp ut control register bit to 1. led drive enable register the led drive enable register ( table 30 ) activates the controlled cu rrent drive. the port c pin must first be enabled by setting the a lternate function register to select the led function. . leden[7:0]?led drive enable these bits determine which port c pins are connected to an internal current sink. table 29. port a?d output data register (p x out) bits 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fd3h, fd7h, fdbh, fdfh table 30. led drive enable (leden) bits 7 6 5 4 3 2 1 0 field leden[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f82h
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 48 0 = tristate the port c pin. 1= enable controlled current sink on the port c pin. led drive level high register the led drive level registers contain tw o control bits for each port c pin ( table 31 ). these two bits select between four programmab le drive levels. each pin is individually programmable. ledlvlh[7:0]?led level high bit {ledlvlh, ledlvll} select one of four programmable current drive levels for each port c pin. 00 = 3 ma 01= 7 ma 10= 13 ma 11= 20 ma led drive level low register the led drive level registers contain tw o control bits for each port c pin ( table 32 ). these two bits select between four programmab le drive levels. each pin is individually programmable. ledlvlh[7:0]?led level high bit {ledlvlh, ledlvll} select one of four programmable current drive levels for each port c pin. table 31. led drive level high register (ledlvlh) bits 7 6 5 4 3 2 1 0 field ledlvlh[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f83h table 32. led drive level low register (ledlvll) bits 7 6 5 4 3 2 1 0 field ledlvll[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f84h
ps022815-0206 general-purpose i/o z8 encore! xp ? 4k series product specification 49 00 = 3 ma 01 = 7 ma 10 = 13 ma 11 = 20 ma
ps022815-0206 interrupt controller z8 encore! xp ? 4k series product specification 50 interrupt controller overview the interrupt controller on the z8 encore! xp ? 4k series products prioritizes the interrupt requests from the on-chip peripherals and the gp io port pins. the features of the interrupt controller include the following: ? 20 unique interrupt vectors: ? 12 gpio port pin interrupt sources (two are shared) ? 10 on-chip peripheral interru pt sources (two are shared) ? flexible gpio interrupts ? eight selectable rising and falling edge gpio interrupts ? four dual-edge interrupts ? three levels of individually programmable interrupt priority ? watch-dog timer and lvd can be conf igured to generate an interrupt interrupt requests (irqs) allow peripheral devi ces to suspend cpu oper ation in an orderly manner and force the cpu to start an interrupt service routine (isr). usually this interrupt service routine is involved with the exchange of data, status information, or control infor- mation between the cpu and the interrupting pe ripheral. when the service routine is com- pleted, the cpu returns to the operation from wh ich it was interrupted. the ez8 cpu supports both vectored and polled interrupt handling. for polled interrupts, the interrupt controller has no effe ct on operation. refer to the ez8 cpu user manual for more information regarding interrupt servicing by the ez8 cpu. the ez8 cpu user man- ual is available for download at www.zilog.com . interrupt vector listing table 33 lists all of the interrupts available in or der of priority. the interrupt vector is stored with the most significant byte (msb) at the even program memory address and the least significant byte (lsb) at the following odd program memory address. some port interrupts are not available on the 8- and 20-pin packages. the adc interrupt is unavailable on devices not containing an adc. note:
ps022815-0206 interrupt controller z8 encore! xp ? 4k series product specification 51 table 33. trap and interrupt vectors in order of priority priority program memory vector address interrupt or trap source highest 0002h reset (not an interrupt) 0004h watch-dog timer (see watch-dog timer chapter) 003ah primary oscillator fa il trap (not an interrupt) 003ch watchdog oscillator fa il trap (not an interrupt) 0006h illegal instruction trap (not an interrupt) 0008h reserved 000ah timer 1 000ch timer 0 000eh uart 0 receiver 0010h uart 0 transmitter 0012h reserved 0014h reserved 0016h adc 0018h port a7, selectable rising or fallin g input edge or lvd (see the chapter reset, stop mode recovery and low voltage detection on page 20 ) 001ah port a6, selectable rising or fa lling input edge or comparator output 001ch port a5, selectable ri sing or falling input edge 001eh port a4, selectable ri sing or falling input edge 0020h port a3 or port d3, selectable rising or falling input edge 0022h port a2 or port d2, selectable rising or falling input edge 0024h port a1, selectable ri sing or falling input edge 0026h port a0, selectable ri sing or falling input edge 0028h reserved 002ah reserved 002ch reserved 002eh reserved 0030h port c3, both input edges 0032h port c2, both input edges 0034h port c1, both input edges
ps022815-0206 interrupt controller z8 encore! xp ? 4k series product specification 52 architecture figure 8 illustrates the interrupt controller block diagram. figure 8.interrupt controller block diagram operation master interrupt enable the master interrupt enable bit ( irqe ) in the interrupt control register globally enables and disables interrupts. interrupts are globally enabled by any of the following actions: ? execution of an ei (enable interrupt) instruction ? execution of an iret (return from interrupt) instruction lowest 0036h port c0, both input edges 0038h reserved table 33. trap and interrupt vectors in order of priority (continued) priority program memory vector address interrupt or trap source vector irq request high priority medium priority low priority priority mux interrupt request latches and control port interrupts internal interrupts
ps022815-0206 interrupt controller z8 encore! xp ? 4k series product specification 53 ? writing a 1 to the irqe bit in the interrupt control register interrupts are globally disabled by any of the following actions: ? execution of a di (disable interrupt) instruction ? ez8 cpu acknowledgement of an interrupt se rvice request from the interrupt controller ? writing a 0 to the irqe bit in the interrupt control register ? reset ? execution of a trap instruction ? illegal instruction trap ? primary oscillator fail trap ? watch-dog oscillator fail trap interrupt vectors and priority the interrupt controller supports three levels of interrupt pr iority. level 3 is the highest priority, level 2 is the second highest priority , and level 1 is the lowest priority. if all of the interrupts are enable d with identical interrupt prior ity (all as level 2 interrupts, for example), the interrupt priori ty is assigned from highest to lowest as specified in table 33 on page 51 . level 3 interrupts are always assigned higher priority than level 2 interrupts which, in turn, always are assigned higher pr iority than level 1 interrupts. within each interrupt priority level (level 1, level 2, or level 3), priority is ass igned as specified in table 33 , above. reset, watch-dog timer interrupt (if enabled), primary oscillator fail trap, watchdog oscillator fail trap, and ille gal instruction trap always have highest (level 3) priority. interrupt assertion interrupt sources assert their interrupt requests for only a single system clock period (sin- gle pulse). when the interrupt request is ac knowledged by the ez8 cpu, the correspond- ing bit in the interrupt request register is cl eared until the next interrupt occurs. writing a 0 to the corresponding bit in the interrupt re quest register likewise clears the interrupt request. the following coding style that clears b its in the interrupt request registers is not rec- ommended. all incoming inte rrupts received between execu tion of the first ldx com- mand and the final ldx command are lost. poor coding style that can result in lost interrupt requests: ldx r0, irq0 and r0, mask ldx irq0, r0 caution:
ps022815-0206 interrupt controller z8 encore! xp ? 4k series product specification 54 to avoid missing interrupts, use the follo wing coding style to clear bits in the interrupt request 0 register: good coding style that avoids lost interrupt requests: andx irq0, mask software interrupt assertion program code can generate interrupts directly. writing a 1 to the correct bit in the interrupt request register triggers an interrupt (assumi ng that interrupt is enabled). when the inter- rupt request is acknowledged by the ez8 cpu, the bit in the interrupt request register is automatically cleared to 0. the following coding style used to generate software interrupts by setting bits in the in- terrupt request registers is not recommended. all incomi ng interrupts received be- tween execution of the first ldx command and the final ldx command are lost. poor coding style that can result in lost interrupt requests: ldx r0, irq0 or r0, mask ldx irq0, r0 to avoid missing interrupts, use the following coding style to set bits in the interrupt re- quest registers: good coding style that avoids lost interrupt requests: orx irq0, mask interrupt control re gister definitions for all interrupts other than the watch-dog timer interrupt, the primary oscillator fail trap, and the watchdog oscillator fail trap, the interrupt control re gisters enable individ- ual interrupts, set interrupt prioritie s, and indicate interrupt requests. interrupt request 0 register the interrupt request 0 (irq0) register ( table 34 ) stores the interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq0 register beco mes 1. if interrupts are globally enabled (vec- tored interrupts), the interrupt controller passe s an interrupt request to the ez8 cpu. if caution: caution: caution:
ps022815-0206 interrupt controller z8 encore! xp ? 4k series product specification 55 interrupts are globally disabl ed (polled interrupts), the ez8 cpu can read the interrupt request 0 register to determine if any interrupt requests are pending. reserved?must be 0. t1i?timer 1 interrupt request 0 = no interrupt request is pending for timer 1. 1 = an interrupt request from timer 1 is awaiting service. t0i?timer 0 interrupt request 0 = no interrupt request is pending for timer 0. 1 = an interrupt request from timer 0 is awaiting service. u0rxi?uart 0 receiver interrupt request 0 = no interrupt request is pe nding for the uart 0 receiver. 1 = an interrupt request from the ua rt 0 receiver is awaiting service. u0txi?uart 0 transmitter interrupt request 0 = no interrupt request is pending for the uart 0 transmitter. 1 = an interrupt request from the ua rt 0 transmitter is awaiting service. adci?adc interrupt request 0 = no interrupt request is pending for the analog-to-digital converter. 1 = an interrupt request from the analog-t o-digital converter is awaiting service. interrupt request 1 register the interrupt request 1 (irq1) register ( table 35 ) stores interrupt requ ests for both vec- tored and polled interrupts. when a request is presented to the interrupt controller, the cor- responding bit in the irq1 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an in terrupt request to the ez8 cpu. if interrupts are globally disabled (polled interrupts), th e ez8 cpu can read the interrupt request 1 register to determine if any interrupt requests are pending. table 34. interrupt request 0 register (irq0) bits 7 6 5 4 3 2 1 0 field reserved t1i t0i u0rxi u0txi reserved reserved adci reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc0h
ps022815-0206 interrupt controller z8 encore! xp ? 4k series product specification 56 pa 7v i?port a7 or lvd interrupt request 0 = no interrupt request is pending for gpio port a or lvd. 1 = an interrupt request from gpio port a or lvd. pa6ci?port a6 or comparator interrupt request 0 = no interrupt request is pendin g for gpio port a or comparator. 1 = an interrupt request from gpio port a or comparator. pa x i?port a pin x interrupt request 0 = no interrupt request is pending for gpio port a pin x . 1 = an interrupt request from gpio port a pin x is awaiting service. where x indicates the specific gp io port pin number (0?5). interrupt request 2 register the interrupt request 2 (irq2) register ( table 36 ) stores interrupt requ ests for both vec- tored and polled interrupts. when a request is presented to the interrupt controller, the cor- responding bit in the irq2 register becomes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller passes an in terrupt request to the ez8 cpu. if interrupts are globally disabled (polled interrupts), th e ez8 cpu can read the interrupt request 2 register to determine if any interrupt requests are pending. reserved?must be 0. pc x i?port c pin x interrupt request 0 = no interrupt request is pending for gpio port c pin x . 1 = an interrupt request from gpio port c pin x is awaiting service. where x indicates the specific gpio port c pin number (0?3). table 35. interrupt request 1 register (irq1) bits 7 6 5 4 3 2 1 0 field pa7vi pa6ci pa5i pa4i pa3i pa2i pa1i pa0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc3h table 36. interrupt request 2 register (irq2) bits 7 6 5 4 3 2 1 0 field reserved pc3i pc2i pc1i pc0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc6h
ps022815-0206 interrupt controller z8 encore! xp ? 4k series product specification 57 irq0 enable high and low bit registers table 37 describes the priority co ntrol for irq0. the irq0 en able high and low bit reg- isters ( tables 38 and 39 ) form a priority encoded enablin g for interrupts in the interrupt request 0 register. reserved?must be 0. t1enh?timer 1 interrupt re quest enable high bit t0enh?timer 0 interrupt re quest enable high bit u0renh?uart 0 receive interrupt request enable high bit u0tenh?uart 0 transmit interrupt request enable high bit adcenh?adc interrupt request enable high bit reserved?must be 0. table 37. irq0 enable and priority encoding irq0enh[ x ] irq0enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 medium 1 1 level 3 high where x indicates the register bits from 0?7. table 38. irq0 enable high bit register (irq0enh) bits 7 6 5 4 3 2 1 0 field reserved t1enh t0enh u0renh u0tenh reserved reserved adcenh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc1h table 39. irq0 enable low bit register (irq0enl) bits 7 6 5 4 3 2 1 0 field reserved t1enl t0enl u0renl u0 tenl reserved reserved adcenl reset 00000000 r/w r r/w r/w r/w r/w r r r/w addr fc2h
ps022815-0206 interrupt controller z8 encore! xp ? 4k series product specification 58 t1enl?timer 1 interrupt request enable low bit t0enl?timer 0 interrupt request enable low bit u0renl?uart 0 receive interru pt request enable low bit u0tenl?uart 0 transmit interrupt request enable low bit adcenl?adc interrupt request enable low bit irq1 enable high and low bit registers table 40 describes the priority co ntrol for irq1. the irq1 en able high and low bit reg- isters ( tables 41 and 42 ) form a priority encoded enablin g for interrupts in the interrupt request 1 register. pa7venh?port a bit[7] or lvd in terrupt request enable high bit pa6cenh?port a bit[7] or comparator interrupt request enable high bit pa x enh?port a bit[ x ] interrupt request enable high bit refer to the shared interrupt select (irqss) re gister for selection of either the lvd or the comparator as the interrupt source. table 40. irq1 enable and priority encoding irq1enh[ x ]irq1enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 medium 11 level 3 high where x indicates the register bits from 0?7. table 41. irq1 enable high bit register (irq1enh) bits 7 6 5 4 3 2 1 0 field pa7venh pa6cenh pa5enh pa4enh pa3enh pa2enh pa1enh pa0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc4h
ps022815-0206 interrupt controller z8 encore! xp ? 4k series product specification 59 pa7venl?port a bit[7] or lvd interrupt request enable low bit pa6cenl?port a bit[6] or comparator interrupt request enable low bit pa x enl?port a bit[ x ] interrupt reques t enable low bit irq2 enable high and low bit registers table 43 describes the priority co ntrol for irq2. the irq2 en able high and low bit reg- isters ( tables 44 and 45 ) form a priority encoded enablin g for interrupts in the interrupt request 2 register. reserved?must be 0. c3enh?port c3 interrupt request enable high bit c2enh?port c2 interrupt request enable high bit table 42. irq1 enable low bit register (irq1enl) bits 7 6 5 4 3 2 1 0 field pa7venl pa6cenl pa5enl pa4enl pa3enl pa2enl pa1enl pa0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc5h table 43. irq2 enable and priority encoding irq2enh[ x ]irq2enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 medium 1 1 level 3 high where x indicates the register bits from 0?7. table 44. irq2 enable high bit register (irq2enh) bits 7 6 5 4 3 2 1 0 field reserved c3enh c2enh c1enh c0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc7h
ps022815-0206 interrupt controller z8 encore! xp ? 4k series product specification 60 c1enh?port c1 interrupt request enable high bit c0enh?port c0 interrupt request enable high bit reserved?must be 0. c3enl?port c3 interrupt request enable low bit c2enl?port c2 interrupt request enable low bit c1enl?port c1 interrupt request enable low bit c0enl?port c0 interrupt request enable low bit interrupt edge select register the interrupt edge sele ct (irqes) register ( table 46 ) determines whether an interrupt is generated for the rising edge or falling edge on the selected gpio port a or port d input pin. ies x ?interrupt edge select x 0 = an interrupt request is genera ted on the falling edge of the pa x input or pdx. 1 = an interrupt request is genera ted on the rising edge of the pa x input pdx. where x indicates the specific gpio port pin number (0 through 7). shared interrupt select register the shared interrupt select (irqss) register ( table 47 ) determines the source of the padxs interrupts. the shared interrupt select register selects between port a and alter- nate sources for the individual interrupts. table 45. irq2 enable low bit register (irq2enl) bits 7 6 5 4 3 2 1 0 field reserved c3enl c2enl c1enl c0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc8h table 46. interrupt edge select register (irqes) bits 7 6 5 4 3 2 1 0 field ies7 ies6 ies5 ies4 ies3 ies2 ies1 ies0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fcdh
ps022815-0206 interrupt controller z8 encore! xp ? 4k series product specification 61 because these shared interrupts are edge-trigger ed, it is possible to generate an interrupt just by switching from one shared source to another. for this reason, an interrupt must be disabled before switching between sources. pa7vs?pa 7 /lvd selection 0 = pa 7 is used for the interrupt for pa7vs interrupt request. 1 = the lvd is used for the inte rrupt for pa7vs interrupt request. pa6cs?pa6/comparator selection 0 = pa6 is used for the interru pt for pa6cs interrupt request. 1 = the comparator is used for the interrupt for pa6cs interrupt request. reserved?must be 0. interrupt control register the interrupt control (irqctl) register ( table 48 ) contains the master enable bit for all interrupts. irqe?interrupt request enable this bit is set to 1 by executing an ei (e nable interrupts) or iret (interrupt return) instruction, or by a direct register write of a 1 to this bit. it is reset to 0 by executing a di instruction, ez8 cpu acknowledgement of an in terrupt request, reset or by a direct regis- ter write of a 0 to this bit. 0 = interrupts are disabled. 1 = interrupts are enabled. reserved?must be 0. table 47. shared interrupt select register (irqss) bits 7 6 5 4 3 2 1 0 field pa7vs pa6cs reserved reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fceh table 48. interrupt control register (irqctl) bits 7 6 5 4 3 2 1 0 field irqe reserved reset 00000000 r/w r/wrrrrrrr addr fcfh
ps022815-0206 timers z8 encore! xp ? 4k series product specification 62 timers overview these z8 encore! xp ? 4k series products contain two 16-bit reloadable timers that can be used for timing, event counting, or ge neration of pulse-width modulated (pwm) sig- nals. the timers? features include: ? 16-bit reload counter ? programmable prescaler with pr escale values from 1 to 128 ? pwm output generation ? capture and compare capability ? external input pin for timer input, clock gating, or capture signal. external input pin signal frequency is limited to a maximum of on e-fourth the system clock frequency. ? timer output pin ? timer interrupt in addition to the timers described in this ch apter, the baud rate generator of the uart (if unused) may also provide basic timing functionality. refer to chapter uart on page 89 for information about using the baud rate generator as an additional timer. architecture figure 9 illustrates the architecture of the timers.
ps022815-0206 timers z8 encore! xp ? 4k series product specification 63 figure 9.timer block diagram operation the timers are 16-bit up-counters. minimum tim e-out delay is set by loading the value 0001h into the timer reload high and low by te registers and setting the prescale value to 1. maximum time-out delay is set by loading the value 0000h into the timer reload high and low byte registers and setting the prescale value to 128. if the timer reaches ffff h , the timer rolls over to 0000 h and continues counting. timer operating modes the timers can be configured to operate in the following modes: one-shot mode in one-shot mode, the timer counts up to th e 16-bit reload value stored in the timer reload high and low byte registers. the timer input is the system clock. upon reaching the reload value, the timer generates an interrupt and th e count value in the timer high and low byte registers is reset to 0001 h . the timer is automatica lly disabled and stops counting. also, if the timer output alternate function is enabled, the timer output pin changes state for one system clock cycle (from low to high or from high to low) upon timer reload. if 16-bit pwm/compare 16-bit counter with prescaler 16-bit reload register timer control compare compare interrupt, pwm, and timer output control timer timer block system timer data block output control bus clock input gate input capture input timer interrupt timer output complement
ps022815-0206 timers z8 encore! xp ? 4k series product specification 64 it is appropriate to have the timer output ma ke a state change at a one-shot time-out (rather than a single cycle pulse), first set th e tpol bit in the timer control register to the start value before enabling one-shot mode. after starting the timer, set tpol to the opposite bit value. the steps for configuring a timer for one-shot mode and initiating the count are as fol- lows: 1. write to the timer control register to: ? disable the timer ? configure the timer for one-shot mode. ? set the prescale value. ? set the initial output level (high or lo w) if using the timer output alternate function. 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in one-shot mode, the system clock always provides the timer input. the timer period is given by the following equation: continuous mode in continuous mode, the timer counts up to the 16-bit reload va lue stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the reload value, the timer generate s an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate func tion is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. the steps for conf iguring a timer for continuous mo de and initiating the count are as follows: 1. write to the timer control register to: ? disable the timer ? configure the timer for continuous mode. ? set the prescale value. one-shot mode time-out period (s) reload value start value ? () prescale system clock frequency (hz) ------------------------------------------------------------------------------------------------- =
ps022815-0206 timers z8 encore! xp ? 4k series product specification 65 ? if using the timer output alternate functio n, set the initial output level (high or low). 2. write to the timer high and low byte regist ers to set the starting count value (usually 0001h ). this action only affects the first p ass in continuous mode. after the first timer reload in continuous mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt (if appropriate ) and set the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pin (i f using the timer output function) for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in continuous mode, the system clock alwa ys provides the timer input. the timer period is given by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equatio n to determine the first time-out period. counter mode in counter mode, the timer co unts input transitions from a gpio port pin. the timer input is taken from the gpio po rt pin timer input alternate function. the tpol bit in the timer control register selects whether the coun t occurs on the rising edge or the falling edge of the timer input signal. in c ounter mode, the prescaler is disabled. the input frequency of the timer input sign al must not exceed one-fourth the system clock frequency. further, the high or low stat e of the input signal pulse must be no less than twice the system clock period. a shorter pulse may not be captured. upon reaching the reload value stored in the timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. the steps for configuring a timer for coun ter mode and initiating the count are as fol- lows: 1. write to the timer control register to: ? disable the timer ? configure the timer for counter mode continuous mode time-out period (s) reload value prescale system clock frequency (hz) ---------------------------------------------------------------------------- = caution:
ps022815-0206 timers z8 encore! xp ? 4k series product specification 66 ? select either the rising edge or falling edge of the timer input signal for the count. this selection also sets the initial logic le vel (high or low) for the timer output alternate function. however, the timer ou tput function is not required to be enabled. 2. write to the timer high and low byte regi sters to set the startin g count value. this only affects the first pass in counter mode. after the first timer reload in counter mode, counting always begins at the reset value of 0001h . in counter mode the timer high and low byte regi sters must be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer. in counter mode, the number of timer input transitions since the timer start is given by the following equation: comparator counter mode in comparator counter mode , the timer counts input tr ansitions from the analog comparator output. the tpol bit in the timer control register selects whether the count occurs on the rising edge or the falling edge of the comparator output signal. in compar- ator counter mode, the prescaler is disabled. the frequency of the comparator output sign al must not exceed one-fourth the system clock frequency. further, the high or low st ate of the comparator output signal pulse must be no less than twice the system cloc k period. a shorter pulse may not be captured. after reaching the reload value stored in th e timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. the steps for configuring a timer for co mparator counter mode and initiating the count are as follows: 1. write to the timer control register to: ? disable the timer counter mode timer input transition s current count value start value ? = caution:
ps022815-0206 timers z8 encore! xp ? 4k series product specification 67 ? configure the timer for comparator counter mode ? select either the rising edge or falling edge of the comparator output signal for the count. this also sets the initial logic le vel (high or low) for the timer output alternate function. however, the timer ou tput function is not required to be enabled. 2. write to the timer high and low byte regi sters to set the startin g count value. this action only affects the first pass in co mparator counter mode. after the first timer reload in comparator counter mode, counting always begins at the reset value of 0001h . generally, in comparator counter mode the timer high and low byte registers mu st be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer. in comparator counter mode, the number of comparator output transitions since the timer start is given by the following equation: pwm single output mode in pwm single output mode, the timer outputs a pulse-width modulator (pwm) output signal through a gpio port pin. the timer input is the system clock. the timer first counts up to the 16-bit pwm match value st ored in the timer pwm high and low byte registers. when the timer count value matche s the pwm value, the timer output toggles. the timer continues coun ting until it reaches the reload va lue stored in th e timer reload high and low byte registers. upon reaching the reload va lue, the timer generates an interrupt, the count value in the timer hi gh and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and transitions to a low (0) when the timer value match es the pwm value. the timer output signal returns to a high (1) after the timer re aches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and transitions to a high (1) when the timer value match es the pwm value. the timer output signal returns to a low (0) after the timer reaches the reload value and is reset to 0001h . comparator output transitions current count value start value ? =
ps022815-0206 timers z8 encore! xp ? 4k series product specification 68 the steps for configuring a timer for pwm single output mode and initiating the pwm operation are as follows: 1. write to the timer control register to: ? disable the timer ? configure the timer for pwm single output mode. ? set the prescale value. ? set the initial logic level (high or lo w) and pwm high/low transition for the timer output alternate function. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). this only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the timer reload high and low by te registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 5. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer and initiate counting. the pwm period is represented by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equation to determine the first pwm time-out period. if tpol is set to 0, the ratio of the pwm outp ut high time to the total period is repre- sented by: if tpol is set to 1, the ratio of the pwm outp ut high time to the total period is repre- sented by: pwm period (s) reload value prescale system clock frequency (hz) ---------------------------------------------------------------------------- = pwm output high time ratio (%) reload value pwm value ? reload value ----------------------------------------------------------------------- - 100 = pwm output high time ratio (%) pwm value reload value ---------------------------------- 100 =
ps022815-0206 timers z8 encore! xp ? 4k series product specification 69 pwm dual output mode in pwm dual output mode, the timer outpu ts a pulse-width modulated (pwm) out- put signal pair (basic pwm signal and its co mplement) through two gpio port pins. the timer input is the system clock. the timer fi rst counts up to the 16-bit pwm match value stored in the timer pwm high and low byte registers. when the timer count value matches the pwm value, the timer output t oggles. the timer con tinues counting until it reaches the reload value stored in the timer reload high and low byte registers. upon reaching the reload value, the timer generate s an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and transitions to a low (0) when the timer value match es the pwm value. the timer output signal returns to a high (1) after the timer re aches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and transitions to a high (1) when the timer value match es the pwm value. the timer output signal returns to a low (0) after the timer reaches the reload value and is reset to 0001h . the timer also generates a second pwm outp ut signal timer output complement. the timer output complement is the complement of the timer output pwm signal. a pro- grammable deadband delay can be configured to time delay (0 to 128 system clock cycles) pwm output transitions on these two pins from a low to a high (inactive to active). this ensures a time gap between the deassertion of one pwm output to the assertion of its com- plement. the steps for configuring a timer for pwm dual output mode and initiating the pwm operation are as follows: 1. write to the timer control register to: ? disable the timer ? configure the timer for pwm dual outp ut mode by writing the tmode bits in the txctl1 register and thetmodehi bit in txctl0 register. ? set the prescale value. ? set the initial logic level (high or lo w) and pwm high/low transition for the timer output alternate function. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). this only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the pwm control register to set the pwm dead band delay value. the deadband delay must be less th an the duration of the pos itive phase of the pwm signal (as defined by the pwm high and low byte re gisters). it must also be less than the
ps022815-0206 timers z8 encore! xp ? 4k series product specification 70 duration of the negative phase of the pw m signal (as defined by the difference between the pwm registers and the timer reload registers). 5. write to the timer reload high and low by te registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 6. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 7. configure the associated gpio port pin for the timer output and timer output complement alternate functio ns. the timer output comple ment function is shared with the timer input function for both tim ers. setting the timer mode to dual pwm automatically switches the function from timer in to timer out complement. 8. write to the timer control register to enable the timer and initiate counting. the pwm period is represented by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation determines the first pwm time-out period. if tpol is set to 0, the ratio of the pwm outp ut high time to the total period is repre- sented by: if tpol is set to 1, the ratio of the pwm outp ut high time to the total period is repre- sented by: capture mode in capture mode, the current timer count valu e is recorded when the appropriate exter- nal timer input transition occu rs. the capture count value is written to the timer pwm high and low byte registers. the timer inpu t is the system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a falling edge of the timer input signal. when the capture ev ent occurs, an interrupt is generated and the timer continues counting. the inpcap bit in tx ctl0 register is set to indicate the timer interrupt is because of an input capture event. the timer continues coun ting up to the 16-bit reload valu e stored in the timer reload high and low byte registers. upon reaching the reload va lue, the timer generates an pwm period (s) reload value prescale system clock frequency (hz) ---------------------------------------------------------------------------- = pwm output high time ratio (%) reload value pwm value ? reload value ----------------------------------------------------------------------- - 100 = pwm output high time ratio (%) pwm value reload value ---------------------------------- 100 =
ps022815-0206 timers z8 encore! xp ? 4k series product specification 71 interrupt and continues counting. the inpcap bit in txctl0 register clears indicating the timer interrupt is not because of an input capture event. the steps for configuring a timer for captur e mode and initiating the count are as fol- lows: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture mode. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . clearing these registers allows user software to determin e if interrupts were ge nerated by either a capture event or a reload. if the pwm high and low byte registers still contain 0000h after the interrupt, the interru pt was generated by a reload. 5. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input capture and reload events. if appropri ate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting ticonfig field of the txctl0 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. in capture mode, the elapsed time from timer start to capture event can be calculated using the following equation: capture restart mode in capture restart mode, the current timer count value is recorded when the accept- able external timer input transition occurs. the capture count value is written to the timer pwm high and low byte registers. th e timer input is the system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a falling edge of the timer input signal. when the capture event occurs, an interrupt is generated and the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txc tl0 register is set to indicate the timer interrupt is because of an input capture event. capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) ---------------------------------------------------------------------------------------------------- =
ps022815-0206 timers z8 encore! xp ? 4k series product specification 72 if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txctl0 register is cleared to indicate the timer interrupt is not cause d by an input capture event. the steps for configuring a timer for capt ure restart mode and initiating the count are as follows: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture rest art mode by writing the tmode bits in the txctl1 register and the tmodehi bit in txctl0 register. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . this allows user software to determine if interrupts were generated by either a capture event or a reload. if the pwm high and lo w byte registers still contain 0000h after the interrupt, the interrupt wa s generated by a reload. 5. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input capture and reload events. if appropri ate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting ticonfig field of the txctl0 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. in capture mode, the elapsed time from timer start to capture event can be calculated using the following equation: compare mode in compare mode, the timer counts up to the 16-bit maximum compare value stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the compare value, the timer genera tes an interrupt and co unting continues (the timer value is not reset to 0001h ). also, if the timer output alternate function is enabled, capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) ---------------------------------------------------------------------------------------------------- =
ps022815-0206 timers z8 encore! xp ? 4k series product specification 73 the timer output pin changes state (from low to high or from high to low) upon com- pare. if the timer reaches ffff h , the timer rolls over to 0000 h and continue counting. the steps for configuring a timer for compar e mode and initiating th e count are as fol- lows: 1. write to the timer control register to: ? disable the timer ? configure the timer for compare mode. ? set the prescale value. ? set the initial logic level (high or low) fo r the timer output alternate function, if appropriate. 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the compare value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in compare mode, the system clock always provides the timer input. the compare time can be calculated by the following equation: gated mode in gated mode, the timer counts only when the timer input si gnal is in its active state (asserted), as determined by the tpol bit in the timer control register. when the timer input signal is asserted, counting begins. a timer interrupt is generated when the timer input signal is deasserted or a timer reload occurs. to determine if a timer input signal deassertion generated the interrupt, read the as sociated gpio input value and compare to the value stored in the tpol bit. the timer counts up to the 16 -bit reload value stored in th e timer reload high and low byte registers. the timer input is the system clock. when r eaching the relo ad value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes (assuming the ti mer input signal remains asserted). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from hi gh to low) at timer reset. the steps for configuring a tim er for gated mode and initiatin g the count are as follows: compare mode time (s) compare value start value ? () prescale system clock frequency (hz) ------------------------------------------------------------------------------------------------------- =
ps022815-0206 timers z8 encore! xp ? 4k series product specification 74 1. write to the timer control register to: ? disable the timer ? configure the timer for gated mode. ? set the prescale value. 2. write to the timer high and low byte regist ers to set the starting count value. writing these registers only affects the first pass in gated mode. after the first timer reset in gated mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input deassertion and reload events. if appropri ate, configure the timer interrupt to be generated only at the input deassertion even t or the reload event by setting ticonfig field of the txctl0 register. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control register to enable the timer. 7. assert the timer input signal to initiate the counting. capture/compare mode in capture/compare mode, the timer begins counting on the first external timer input transition. the acceptable transition (ri sing edge or falling edge) is set by the tpol bit in the timer control register. th e timer input is th e system clock. every subsequent acceptable transition (after the first) of the timer input signal captures the current count value. the capture valu e is written to the timer pwm high and low byte registers. when the capt ure event occurs, an interrupt is generated, the count value in the timer high and low byte registers is reset to 0001h , and counting resumes. the inpcap bit in txctl0 register is set to indicat e the timer interrupt is caused by an input capture event. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the compare value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txctl0 register is cleared to indicate the timer interrupt is not because of an input capture event. the steps for configuring a timer for capture/compare mode and initiating the count are as follows: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture/compare mode. ? set the prescale value.
ps022815-0206 timers z8 encore! xp ? 4k series product specification 75 ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the compare value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt registers.by defau lt, the timer interrupt are generated for both input capture and reload events. if appropri ate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting ticonfig field of the txctl0 register. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control register to enable the timer. 7. counting begins on the first appropriate transition of the timer input signal. no interrupt is generated by this first edge. in capture/compare mode, the elapsed time from timer start to capture event can be calculated using the following equation: reading the timer count values the current count va lue in the timers can be read while counting (enabled). this capability has no effect on timer operation. when the timer is enabled and the timer high byte reg- ister is read, the contents of the timer low byte register are placed in a holding register. a subsequent read from the timer low byte register returns the value in the holding register. this operation allows accurate reads of the full 16-bit time r count value while enabled. when the timers are not enabled, a read fro m the timer low byte register returns the actual value in the counter. timer pin signal operation timer output is a gpio port pin alternate function. the timer outp ut is toggled every time the counter is reloaded. the timer input can be used as a selectable counting source. it shares the same pin as the complementary timer output. when selected by the gpio alternate function registers, this pin functions as a timer input in all modes except for the dual pwm output mode. for this mode, there is no timer input available. capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) --------------------------------------------------------------------------------------------------------- =
ps022815-0206 timers z8 encore! xp ? 4k series product specification 76 timer control register definitions timer 0?1 high and low byte registers the timer 0?1 high and low byte (txh and txl) registers ( tables 49 and 39) contain the current 16-bit timer count value. when the timer is enabled, a read from txh causes the value in txl to be stored in a tempor ary holding register. a read from txl always returns this temporary register when the timers are enabled. when the timer is disabled, reads from txl read the register directly. writing to the timer high and low byte regist ers while the timer is enabled is not recom- mended. there are no temporary holding regist ers available for write operations, so simul- taneous 16-bit writes are not possible. if eith er the timer high or low byte registers are written during counting, the 8- bit written value is placed in the counter (high or low byte) at the next clock edge. the coun ter continues counting from the new value. th and tl?timer high and low bytes these 2 bytes, {th[7:0], tl[7:0]}, cont ain the current 16-b it timer count value. timer reload high and low byte registers the timer 0?1 reload high and low byte (txrh and txrl) registers ( tables 51 and 41) store a 16-bit reload value, {trh[7:0], trl[ 7:0]}. values written to the timer reload high byte register are stored in a temporar y holding register. when a write to the timer reload low byte register occurs, the temporar y holding register value is written to the timer high byte register. this operation a llows simultaneous updates of the 16-bit timer table 49. timer 0?1 high byte register (txh) bits 7 6 5 4 3 2 1 0 field th reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f00h, f08h table 50. timer 0?1 low byte register (txl) bits 7 6 5 4 3 2 1 0 field tl reset 00000001 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f01h, f09h
ps022815-0206 timers z8 encore! xp ? 4k series product specification 77 reload value. in compare mode, the timer reload high and low byte registers store the 16-bit compare value. trh and trl?timer reload register high and low these two bytes form the 16-bit reload value, {trh[7:0], trl[ 7:0]}. this value sets the maximum count valu e which initiates a timer reload to 0001h . in compare mode, these two bytes form the 16-bit compare value. timer 0-1 pwm high and low byte registers the timer 0-1 pwm high and low byte (txpwmh and txpwml) registers ( tables 53 and table 54 ) control pulse-width modulator (pwm ) operations. these registers also store the capture values for the capture and capture/compare modes. table 51. timer 0?1 reload high byte register (txrh) bits 7 6 5 4 3 2 1 0 field trh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f02h, f0ah table 52. timer 0?1 reload low byte register (txrl) bits 7 6 5 4 3 2 1 0 field trl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f03h, f0bh table 53. timer 0?1 pwm high byte register (txpwmh) bits 7 6 5 4 3 2 1 0 field pwmh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f04h, f0ch
ps022815-0206 timers z8 encore! xp ? 4k series product specification 78 pwmh and pwml?pulse-width mo dulator high and low bytes these two bytes, {pwmh[7:0], pwml[7:0]}, form a 16-bit value that is compared to the current 16-bit timer count. when a match oc curs, the pwm output changes state. the pwm output value is set by the tpol bit in the timer control register (txctl1) regis- ter. the txpwmh and txpwml registers also st ore the 16-bit captured timer value when operating in capture or capture/compare modes. timer 0?1 control registers time 0?1 control register 0 the timer control register 0 (txctl0) and timer control register 1 (txctl1) deter- mine the timer operating mode. it also in cludes a programmable pwm deadband delay, two bits to configure timer interrupt definitio n, and a status bit to identify if the most recent timer interrupt is caused by an input capture event. tmodehi?timer mode high bit this bit along with the tmode field in txc tl1 register determines the operating mode of the timer. this is the most significant b it of the timer mode selection value. see the txctl1 register description for details of the full timer mode decoding. ticonfig?timer interrupt configuration this field configures timer interrupt definition. table 54. timer 0?1 pwm low byte register (txpwml) bits 7 6 5 4 3 2 1 0 field pwml reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f05h, f0dh table 55. timer 0?1 control register 0 (txctl0) bits 7 6 5 4 3 2 1 0 field tmodehi ticonfig reserved pwmd inpcap reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/w r addr f06h, f0eh
ps022815-0206 timers z8 encore! xp ? 4k series product specification 79 0x = timer interrupt occurs on all de fined reload, compar e and input events 10 = timer interrupt only on defi ned input capture/deassertion events 11 = timer interrupt only on defined reload/compare events reserved?must be 0. pwmd?pwm delay value this field is a programmable delay to contro l the number of system clock cycles delay before the timer output and th e timer output complement are forced to their active state. 000 = no delay 001 = 2 cycles delay 010 = 4 cycles delay 011 = 8 cycles delay 100 = 16 cycles delay 101 = 32 cycles delay 110 = 64 cycles delay 111 = 128 cycles delay inpcap?input capture event this bit indicates if the most recent timer in terrupt is caused by a timer input capture event. 0 = previous timer interrupt is not a result of timer input capture event 1 = previous timer interrupt is a result of timer input capture event timer 0?1 control register 1 the timer 0?1 control (txctl1) registers en able/disable the timers, set the prescaler value, and determine the timer operating mode. ten?timer enable 0 = timer is disabled. 1 = timer enabled to count. tpol?timer input/output polarity operation of this bit is a function of the current operating mode of the timer. one-shot mode when the timer is disabled, the timer output signal is set to the value of this bit. table 56. timer 0?1 control register 1 (txctl1) bits 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f07h, f0fh
ps022815-0206 timers z8 encore! xp ? 4k series product specification 80 when the timer is enabled, the timer outp ut signal is complemented upon timer reload. continuous mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. counter mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. pwm single output mode 0 = timer output is forced low (0) when the timer is disabled. when enabled, the timer output is forced hi gh (1) upon pwm count matc h and forced low (0) upon reload. 1 = timer output is forced high (1) when the timer is disabled. when enabled, the timer output is forced low (0) upon pwm count match and forced high (1) upon reload. capture mode 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the fallin g edge of the timer input signal. compare mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. gated mode 0 = timer counts when the timer input signal is high (1) and interrupts are generated on the falling edge of the timer input. 1 = timer counts when the ti mer input signal is low (0) and interrupts are generated on the rising edge of the timer input. capture/compare mode 0 = counting is started on the first rising edge of the timer input signal. the current count is captured on subsequent risi ng edges of the timer input signal. 1 = counting is started on the first falling ed ge of the timer input signal. the current count is captured on subsequent fa lling edges of the timer input signal. pwm dual output mode 0 = timer output is forced low (0) and time r output complement is forced high (1) when the timer is disabled. when enabled, the timer output is forced high (1) upon pwm count match and forced low (0) upon reload. when enabled, the timer output complement is forced low (0) upon pwm count match an d forced high (1) upon reload. the pwmd field in txctl0 register is a programmable delay to control the
ps022815-0206 timers z8 encore! xp ? 4k series product specification 81 number of cycles time delay before th e timer output and the timer output complement is fo rced to high (1). 1 = timer output is forced high (1) and ti mer output complement is forced low (0) when the timer is disabled. when enabled, the timer output is forced low (0) upon pwm count match and forced high (1) upon reload.when enabled, the timer output complement is forced high (1) upon p wm count match and forced low (0) upon reload. the pwmd field in txctl0 register is a programmable delay to control the number of cycles time delay before th e timer output and the timer output complement is fo rced to low (0). capture restart mode 0 = count is captured on the rising edge of the timer input signal. 1 = count is captured on the fallin g edge of the timer input signal. comparator counter mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. also: 0 = count is captured on the rising edge of the comparator output. 1 = count is captured on the fallin g edge of the comparator output. when the timer output alternate function txout on a gpio port pin is enabled, tx- out will change to whatever state the tpol b it is in.the timer does not need to be en- abled for that to happen. also, the port data direction sub register is not needed to be set to output on txout. changi ng the tpol bit with the tim er enabled and running does not immediately change the txout. pres?prescale value. the timer input clock is divided by 2 pres , where pres can be set from 0 to 7. the pres- caler is reset each time the timer is disabled. this reset ensures proper clock division each time the timer is restarted. 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 tmode?timer mode this field along with the tmodehi bit in txctl0 register determines the operating mode of the timer. tmodehi is the most si gnificant bit of the timer mode selection value. caution:
ps022815-0206 timers z8 encore! xp ? 4k series product specification 82 0000 = one-shot mode 0001 = continuous mode 0010 = counter mode 0011 = pwm single output mode 0100 = capture mode 0101 = compare mode 0110 = gated mode 0111 = capture/compare mode 1000 = pwm dual output mode 1001 = capture restart mode 1010 = comparator counter mode
ps022815-0206 watch-dog timer z8 encore! xp ? 4k series product specification 83 watch-dog timer overview the watch-dog timer (wdt) protects agains t corrupt or unreliab le software, power faults, and other system-level problems which may place the z8 encore! xp ? 4k series devices into unsuitable operating states. th e watch-dog timer includes the following fea- tures: ? on-chip rc oscillator ? a selectable time-out response: reset or interrupt ? 24-bit programmable time-out value operation the watch-dog timer (wdt) is a one-shot timer that resets or interrupts the z8 encore! xp ? 4k series devices when the wdt reaches its terminal count. the watch-dog timer uses a dedicated on-chip rc oscillator as its clock source. the watch-dog timer operates in only two modes: on and off. once enabled, it always counts and must be refreshed to prevent a time-out. perform an enable by ex ecuting the wdt instruction or by setting the wdt_ao flash option bit. the wdt_ao bit forces the watch-dog timer to operate immediately upon reset, even if a wdt instruction has not been executed. the watch-dog timer is a 24-bit reloadable do wncounter that uses three 8-bit registers in the ez8 cpu register space to set the reload value. the nominal wdt time-out period is described by the following equation: where the wdt reload value is the deci mal value of the 24-bit value given by {wdtu[7:0], wdth[7:0], wdtl[7:0]} and th e typical watch-dog timer rc oscillator frequency is 10khz. the watch-dog time r cannot be refreshed after it reaches 000002h . the wdt reload value must no t be set to values below 000004h . table 57 provides information about approxim ate time-out delays for the minimum and maximum wdt reload values. wdt time-out period (ms) wdt reload value 10 ----------------- ------------------ -------------- - =
ps022815-0206 watch-dog timer z8 encore! xp ? 4k series product specification 84 watch-dog timer refresh when first enabled, the watch-dog timer is loaded with the value in the watch-dog timer reload registers. the wa tch-dog timer counts down to 000000h unless a wdt instruction is executed by the ez8 cpu. ex ecution of the wdt instruction causes the downcounter to be reloaded with the wdt re load value stored in the watch-dog timer reload registers. counting resume s following the reload operation. when the z8 encore! xp ? 4k series devices are operating in debug mode (using the on-chip debugger), the watch-dog timer is continuously refreshed to prevent any watch- dog timer time-outs. watch-dog timer time-out response the watch-dog timer times out when the counter reaches 000000h . a time-out of the watch-dog timer generates either an interru pt or a system reset. the wdt_res flash option bit determines the time-out response of the watch-dog timer. refer to the chapter flash option bits on page 148 for information regarding programming of the wdt_res flash option bit. wdt interrupt in normal operation if configured to generate an interrupt when a time-out occurs, the watch-dog timer issues an interrupt request to the interrupt controller and sets the wdt status bit in the reset sta- tus (rststat) register (see page 27 ). if interrupts are enabled, the ez8 cpu responds to the interrupt request by fetching the watch-do g timer interrupt vector and executing code from the vector address. after time-out and interrupt generation, the watch-dog timer counter rolls over to its maximum value of fffffh and continues counting. the watch- dog timer counter is not automatica lly returned to its reload value. the reset status (rststat) register must be read before clearing the wdt interrupt. this read clears the wdt timeout flag and prevents further wdt interrupts from immedi- ately occurring. table 57. watch-dog timer approximate time-out delays wdt reload value (hex) wdt reload value (decimal) approximate time-out delay (with 10khz typical wdt oscillator frequency) typical description 000004 4 400 s minimum time-out delay ffffff 16,777,215 28 minutes maximum time-out delay
ps022815-0206 watch-dog timer z8 encore! xp ? 4k series product specification 85 wdt interrupt in stop mode if configured to generate an interrupt wh en a time-out occurs and the z8 encore! xp ? 4k series devices are in stop mode, the watc h-dog timer automatically initiates a stop mode recovery and generates an interrupt request. both the wdt status bit and the stop bit in the reset status (rststat) register are set to 1 following a wdt time-out in stop mode. refer to the chapter reset, stop mode recovery and low voltage detection on page 20 for more information about stop mode recovery. if interrupts are enabled, follo wing completion of the stop mode recovery the ez8 cpu responds to the interrupt request by fetching the watch-dog timer interrupt vector and executing code from the vector address. wdt reset in normal operation if configured to generate a reset when a tim e-out occurs, the watch-dog timer forces the device into the system reset state. the wd t status bit in the reset status (rststat) register is set to 1. refer to the chapter reset, stop mode recovery and low voltage detection on page 20 for more informatio n about system reset. wdt reset in stop mode if configured to generate a reset when a time- out occurs and the device is in stop mode, the watch-dog timer in itiates a stop mode recovery. bo th the wdt status bit and the stop bit in the reset status (rststat) regist er are set to 1 following wdt time-out in stop mode. refer to the chapter reset, stop mode recovery and low voltage detec- tion on page 20 for more information. watch-dog timer reload unlock sequence writing the unlock sequence to the watch-dog timer (wdtctl) control register address unlocks the three watch-dog timer reload byte registers (wdtu, wdth, and wdtl) to allow changes to the time- out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register. the locking mechanism prevents spurious writes to the reload registers. the fo llowing sequence is required to unlock the watch-dog timer reload byte registers (wdtu, wdth, and wdtl) for write access. 1. write 55 h to the watch-dog timer control register (wdtctl). 2. write aa h to the watch-dog timer control register (wdtctl). 3. write the watch-dog timer reload upper byte register (wdtu). 4. write the watch-dog timer reload high byte register (wdth). 5. write the watch-dog timer reload low byte register (wdtl).
ps022815-0206 watch-dog timer z8 encore! xp ? 4k series product specification 86 all three watch-dog timer reload registers must be written in the order just listed. there must be no other register writes between each of these operations. if a register write occurs, the lock state machine resets and no fu rther writes can occur unless the sequence is restarted. the value in the watch-dog timer re load registers is load ed into the counter when the watch-dog timer is first enabled an d every time a wdt instruction is executed. watch-dog timer calibration due to its extremely low opera ting current, the watch-dog ti mer oscillator is somewhat inaccurate. this variation can be corrected us ing the calibration data stored in the flash information page (see tables 98 and 99 on page 158 ). loading these values into the watch-dog timer reload registers will result in a one-second timeout at room tempera- ture and 3.3v supply voltage. timeouts other than one second may be obtained by scaling the calibration values up or down as required. note that the watch-dog timer accuracy will s till degrade as tempera- ture and supply voltage vary. see table 136, watch-dog timer electrical characteristics and timing on page 220 for details. watch-dog timer contro l register definitions watch-dog timer control register the watch-dog timer control (w dtctl) register is a write-only control register. writ- ing the 55h , aah unlock sequence to the wdtctl re gister address unlocks the three watch-dog timer reload byte registers (w dtu, wdth, and wdtl) to allow changes to the time-out period. these write operatio ns to the wdtctl register address produce no effect on the bits in the wdtctl regist er. the locking mechanism prevents spurious writes to the reload registers. this register address is shared with the read-only reset status register. table 58. watch-dog timer control register (wdtctl) bits 7 6 5 4 3 2 1 0 field wdtunlk reset xxxxxxxx r/w wwwwwwww addr ff0h
ps022815-0206 watch-dog timer z8 encore! xp ? 4k series product specification 87 wdtunlk?watch-dog timer unlock the user software must write the correct unlo cking sequence to this register before it is allowed to modify the contents of the watch-dog timer reload registers. watch-dog timer reload upper, high and low byte registers the watch-dog timer reload upper, high and low byte (wdtu, wdth, wdtl) reg- isters ( tables 59 through 61 ) form the 24-bit reload value th at is loaded into the watch- dog timer when a wdt instruction executes . the 24-bit reload value is {wdtu[7:0], wdth[7:0], wdtl[7:0]}. writing to these registers sets the appropriate reload value. reading from these registers returns the current watch-dog timer count value. the 24-bit wdt reload value must no t be set to a value less than 000004h . wdtu?wdt reload upper byte most significant byte (msb), bits[23: 16], of the 24-bit wdt reload value. wdth?wdt reload high byte middle byte, bits[15:8], of the 24-bit wdt reload value. table 59. watch-dog timer reload upper byte register (wdtu) bits 7 6 5 4 3 2 1 0 field wdtu reset ffh r/w r/w* addr ff1h r/w* - read returns the current wdt count valu e. write sets the appro priate reload value. table 60. watch-dog timer reload high byte register (wdth) bits 7 6 5 4 3 2 1 0 field wdth reset ffh r/w r/w* addr ff2h r/w* - read returns the current wdt count value. write sets the appropriate reload value. caution:
ps022815-0206 watch-dog timer z8 encore! xp ? 4k series product specification 88 wdtl?wdt reload low least significant byte (lsb), bits[7 :0], of the 24-bit wdt reload value. table 61. watch-dog timer reload low byte register (wdtl) bits 7 6 5 4 3 2 1 0 field wdtl reset ffh r/w r/w* addr ff3h r/w* - read returns the current wdt count valu e. write sets the appro priate reload value.
ps022815-0206 uart z8 encore! xp ? 4k series product specification 89 uart overview the universal asynchronous re ceiver/transmitter (uart) is a full-duplex communication channel capable of handling asynchronous data transfers. the uart uses a single 8-bit data mode with selectable parity . features of the uart include: ? 8-bit asynchronous data transfer ? selectable even- and odd-parity generation and checking ? option of one or two stop bits ? separate transmit and receive interrupts ? framing, parity, overrun and break detection ? separate transmit and receive enables ? 16-bit baud rate generator (brg) ? selectable multiprocessor (9-bit) mode wi th three configurable interrupt schemes ? baud rate generator (brg) can be configured and used as a basic 16-bit timer ? driver enable (de) output for external bus transceivers architecture the uart consists of three primary functional blocks: transmitter, rece iver, and baud rate generator. the uart?s transmitter and receiv er function independently, but employ the same baud rate and data format. figure 10 illustrates the uart architecture.
ps022815-0206 uart z8 encore! xp ? 4k series product specification 90 figure 10.uart block diagram operation data format the uart always transmits and receives data in an 8-bit data format, least-significant bit first. an even or odd parity bit can be added to the data stream. each character begins with an active low start bit and ends with either 1 or 2 active high stop bits. figures 11 and 12 illustrates the asynchronous data format employed by the uart without parity and with parity, respectively. receive shifter receive data transmit data transmit shift txd rxd system bus parity checker parity generator receiver control control registers transmitter control cts status register register register register baud rate generator de with address compare
ps022815-0206 uart z8 encore! xp ? 4k series product specification 91 figure 11.uart asynchronous data format without parity figure 12.uart asynchronous data format with parity transmitting data using the polled method follow these steps to transmit data us ing the polled method of operation: 1. write to the uart baud rate high and low byte registers to set the required baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register, if multiprocessor mode is appropriate, to enable multiprocessor (9-bit) mode functions. 4. set the multiprocessor mode select ( mpen ) bit to enable mu ltiprocessor mode. 5. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission ? set the parity enable bit ( pen ), if parity is approp riate and multiprocessor mode is not enabled, and select either even or odd parity ( psel ). ? set or clear the ctse bit to enable or disable control from the remote receiver using the cts pin. start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data field lsb msb idle state of line stop bit(s) 1 2 1 0 start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps022815-0206 uart z8 encore! xp ? 4k series product specification 92 6. check the tdre bit in the uart status 0 register to determine if the transmit data register is empty (indicated by a 1). if empty, continue to step 6. if the transmit data register is full (indicated by a 0), contin ue to monitor the tdre bit until the transmit data register becomes available to receive new data. 7. write the uart control 1 register to select the outgoing address bit. 8. set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 9. write the data byte to the uart transmit data register. the transmitter automatically transfers the data to the transmit sh ift register and transmits the data. 10. make any changes to the multiprocessor bit transmitter ( mpbt ) value, if appropriate and multiprocessor mode is enabled,. 11. to transmit additional bytes, return to step 5. transmitting data using th e interrupt-driven method the uart transmitter interrupt indicates the av ailability of the transmit data register to accept new data for transmission. follow these steps to configure the uart for interrupt- driven data transmission: 1. write to the uart baud rate high and low byte registers to set the appropriate baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart transmitter interrupt and set the acceptable priority. 5. write to the uart control 1 register to enable multiprocessor (9-bit) mode functions, if multiprocessor mode is appropriate. 6. set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. 7. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission ? enable parity, if appropriate and if mu ltiprocessor mode is not enabled, and select either even or odd parity. ? set or clear ctse to enable or disable control fro m the remote receiver using the cts pin. 8. execute an ei instruc tion to enable interrupts.
ps022815-0206 uart z8 encore! xp ? 4k series product specification 93 the uart is now configured for interrupt-d riven data transmission. because the uart transmit data register is empty, an interr upt is generated immediately. when the uart transmit interrupt is detected, the associated interrupt service routine (isr) performs the following: 1. write the uart control 1 register to selec t the multiprocessor bit for the byte to be transmitted: set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 2. write the data byte to the uart transmit data register. the transmitter automatically transfers the data to the transmit sh ift register and transmits the data. 3. clear the uart transmit interrupt bit in th e applicable interrupt request register. 4. execute the iret instruction to return from the interrupt-s ervice routine and wait for the transmit data register to again become empty. receiving data using the polled method follow these steps to configure th e uart for polled data reception: 5. write to the uart baud rate high and low byte registers to set an acceptable baud rate for the incoming data stream. 6. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 7. write to the uart control 1 register to enable multiproc essor mode functions, if appropriate. 8. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if appropriate and if multip rocessor mode is not enabled, and select either even or odd parity. 9. check the rda bit in the uart status 0 re gister to determine if the receive data register contains a valid data byte (indicated by a 1). if rda is set to 1 to indicate available data, continue to step 5. if the rece ive data register is empty (indicated by a 0), continue to monitor the rda bit awaiting reception of the valid data. 10. read data from the uart receive data register. if operati ng in multiprocessor (9-bit) mode, further actions may be re quired depending on the multiprocessor mode bits mpmd[1:0]. 11. return to step 4 to receive additional data.
ps022815-0206 uart z8 encore! xp ? 4k series product specification 94 receiving data using the interrupt-driven method the uart receiver interrupt indicates the availa bility of new data (as well as error condi- tions). follow these steps to configure the uart receiver for interrupt-driven operation: 1. write to the uart baud rate high and low byte registers to set the acceptable baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart receiver interrupt and set the acceptable priority. 5. clear the uart receiver interrupt in th e applicable interrupt request register. 6. write to the uart control 1 register to enable multiprocessor (9-bit) mode functions, if appropriate. ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. ? set the multiprocessor mode bits, mpmd[1:0] , to select the acceptable address matching scheme. ? configure the uart to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for z8 encore! ? devices without a dma block) 7. write the device address to the address compare register (automatic multiprocessor modes only). 8. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if appropriate and if multip rocessor mode is not enabled, and select either even or odd parity. 9. execute an ei instruc tion to enable interrupts. the uart is now configured for interrupt-driven data reception. when the uart receiver interrupt is detected, the associat ed interrupt service rou tine (isr) performs the following: 1. checks the uart status 0 register to dete rmine the source of the interrupt - error, break, or received data. 2. reads the data from the uart receive data register if the interrupt was because of data available. if operating in multiproc essor (9-bit) mode, further actions may be required depending on the mult iprocessor mode bits mpmd[1:0]. 3. clears the uart receiver interrupt in th e applicable interrupt request register.
ps022815-0206 uart z8 encore! xp ? 4k series product specification 95 4. executes the iret instruction to return from the interrupt-service routine and await more data. clear to send (cts ) operation the cts pin, if enabled by the ctse bit of the uart control 0 register, performs flow control on the outgoing transmit datastream. the clear to send (cts ) input pin is sam- pled one system clock before beginning any new character transmission. to delay trans- mission of the next data character, an external receiver must deassert cts at least one system clock cycle before a new data transm ission begins. for multiple character trans- missions, this action is typically perform ed during stop bit transmission. if cts deasserts in the middle of a character transmission, the current character is sent completely. multiprocessor (9-bit) mode the uart has a multiprocessor (9-bit) mode that uses an extra (9th) bit for selec- tive communication when a number of proce ssors share a common uart bus. in multi- processor mode (also referred to as 9- bit mode), the multiprocessor bit ( mp ) is transmitted immediately following the 8-bits of data and immediately preceding the stop bit(s) as illustrated in figure 13 . the character format is: figure 13.uart asynchronous mult iprocessor mode data format in multiprocessor (9-bit) mode, the parity bit location (9th bit) becomes the multi- processor control bit. the uart control 1 and status 1 registers provide multipro- cessor (9-bit) mode control and status information. if an automatic address matching scheme is enabled, the uart ad dress compare register holds the network address of the device. multiprocessor (9-bit) mode receive interrupts when multiprocessor mode is enabled, the uart only processes frames addressed to it. the determination of whether a frame of data is addressed to the uart can be made in hardware, software or so me combination of the two, depending on the multiprocessor configuration bits. in general, the address co mpare feature reduces the load on the cpu, because it does not require access to the uart when it receives data directed to other start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 mp data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps022815-0206 uart z8 encore! xp ? 4k series product specification 96 devices on the multi-node network. the fo llowing three multip rocessor modes are available in hardware: ? interrupt on all address bytes ? interrupt on matched address byte s and correctly framed data bytes ? interrupt only on correctly framed data bytes these modes are selected with mpmd[1:0] in the uart control 1 register. for all mul- tiprocessor modes, bit mpen of the uart control 1 register must be set to 1. the first scheme is enabled by writing 01b to mpmd[1:0]. in this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. the interrupt service routine must manually check the addre ss byte that caused triggered the interrupt. if it matches the uart address, the software clears mpmd[0]. each new incoming byte interrupts the cpu. the software is responsib le for determining the end of the frame. it checks for the end-o f-frame by reading the mprx bit of the uart status 1 register for each incoming byte. if mprx =1, a new frame has begun. if the address of this new frame is different from the uart?s address, mpmd[0] must be set to 1 causing the uart inter- rupts to go inactive until the next address byte. if the new frame?s address matches the uart?s, the data in the new frame is processed as well. the second scheme requires th e following: set mpmd[1:0] to 10b and write the uart?s address into the uart address co mpare register. this mode introduces additional hard- ware control, interrupting only on frames that match the uart?s address. when an incoming address byte does no t match the uart?s address, it is ignored. all successive data bytes in this frame are also ignored. wh en a matching address byte occurs, an inter- rupt is issued and further interrupts now occu r on each succesive data byte. when the first data byte in the frame is read, the newfrm bit of the uart status 1 register is asserted. all successive data bytes have newfrm =0. when the next address byte occurs, the hard- ware compares it to the uart?s address. if th ere is a match, the interrupts continues and the newfrm bit is set for the first byte of the new frame. if there is no match, the uart ignores all incoming bytes un til the next address match. the third scheme is enable d by setting mpmd[1:0] to 11b and by writing the uart?s address into the uart address co mpare register. this mode is identical to the second scheme, except that there are no interrupts on address bytes. the first data byte of each frame remains accompanied by a newfrm assertion. external driver enable the uart provides a driver enable (de) si gnal for off-chip bus transceivers. this fea- ture reduces the software overhead associated with using a gpio pin to control the trans- ceiver when communicatin g on a multi-transceiver bus, such as rs-485. driver enable is an active high signal that envelopes the entire transmitted data frame including parity and stop bits as illustrated in figure 14 . the driver enable signal asserts when a byte is written to the uart transmit data register. the driver enable signal
ps022815-0206 uart z8 encore! xp ? 4k series product specification 97 asserts at least one uart bit period and no greater than two uart bit periods before the start bit is transmitted. this allows a setup time to enable the transceiver. the driver enable signal deasserts one system clock period after the final stop bit is transmitted. this one system clock delay allows both time for da ta to clear the transc eiver before disabling it, as well as the ability to dete rmine if another character follo ws the current character. in the event of back to back char acters (new data must be writte n to the transmit data regis- ter before the previous character is completely transmitted) the de signal is not deasserted between characters. the depol bit in the uart control register 1 sets the polarity of the driver enable signal. figure 14.uart driver enable signal timi ng (shown with 1 stop bit and parity) the driver enable to start bit setup time is calculated as follows: uart interrupts the uart features separate interrupts for the transmitter and the rece iver. in addition, when the uart primary functionality is disable d, the baud rate generator can also func- tion as a basic timer with interrupt capability. transmitter interrupts the transmitter generates a single interrupt when the transmit data register empty bit ( tdre ) is set to 1. this indicates that the tran smitter is ready to acce pt new data for trans- mission. the tdre interrupt occurs after the transmit shift register has shifted the first bit of data out. the transmit data register can now be written with the next character to send. this action provides 7 bit periods of la tency to load the transmit data register before the transmit shift register completes shifting the current character. writing to the uart transmit data register clears the tdre bit to 0. start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit 1 1 0 0 1 de 1 baud rate (hz) ------------------- ------------------ ?? ?? de to start bit setup time (s) 2 baud rate (hz) ------------------- ------------------ ?? ?? ?
ps022815-0206 uart z8 encore! xp ? 4k series product specification 98 receiver interrupts the receiver generates an interrupt when any of the following occurs: ? a data byte is received and is available in the uart receive data register. this interrupt can be disabled independently of the other rece iver interrupt sources. the received data in- terrupt occurs after the receive character has been received and placed in the receive data register. to avoid an overrun error, software must respond to this re ceived data available condition before the next charac ter is completely received. in multiprocessor mode ( mpen = 1), the receive data in terrupts are dependent on the multiprocessor configuration and the most recent address byte. ? a break is received ? an overrun is detected ? a data framing error is detected uart overrun errors when an overrun error conditio n occurs the uart prevents overwriting of the valid data currently in the receive data register. the br eak detect and overrun status bits are not displayed until after the va lid data has been read. after the valid data has been read, the uart st atus 0 register is updated to indicate the overrun condition (and break detect, if applicable). the rda bit is set to 1 to indicate that the receive data register contains a data byte. however, because the overrun error occurred, this byte may not contain valid da ta and must be ignored. the brkd bit indi- cates if the overrun was caused by a break condition on the line. after reading the status byte indicating an overrun error, the receive data register must be read again to clear the error bits is the uart status 0 register. upda tes to the receive data register occur only when the next data word is received. uart data and error handling procedure figure 15 illustrates the recommended procedure fo r use in uart receiver interrupt ser- vice routines. note:
ps022815-0206 uart z8 encore! xp ? 4k series product specification 99 figure 15.uart re ceiver interrupt service routine flow baud rate generator interrupts if the baud rate generator (brg) interrupt enable is set, the uart receiver interrupt asserts when the uart baud rate generator reloads. this conditio n allows the baud rate generator to function as an additiona l counter if the uart functionality is not employed. uart baud rate generator the uart baud rate generator creates a lowe r frequency baud rate clock for data trans- mission. the input to the baud rate generator is the system clock. the uart baud rate high and low byte registers combine to cr eate a 16-bit baud rate divisor value receiver errors? no yes read status discard data read data which interrupt receiver ready clears rda bit and resets error bits read data
ps022815-0206 uart z8 encore! xp ? 4k series product specification 100 (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. the uart data rate is calculated usin g the following equation: when the uart is disabled, the baud rate generator functions as a basic 16-bit timer with interrupt on time-out. to configure the ba ud rate generator as a timer with interrupt on time-out, complete the following procedure: 1. disable the uart by clearing the ren and te n bits in the uart control 0 register to 0. 2. load the acceptable 16-bit count value into the uart ba ud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the birq bit in the uart control 1 register to 1. when configured as a general purpose timer, th e interrupt interval is calculated using the following equation: interrupt interval (s) = system clock period (s) brg[15:0] ] uart control register definitions the uart control registers support the uart and the associated infrared encoder/ decoders. for more inform ation about the infrared op eration, refer to the infrared encoder/decoder chapter on page 109 . uart transmit data register data bytes written to the uart tr ansmit data (uxtxd) register ( table 62 ) are shifted out on the txdx pin. the write-only uart transmit data register shares a register file address with the read-only uart receive data register. table 62. uart transmit data register (u0txd) bits 7 6 5 4 3 2 1 0 field txd reset xxxxxxxx r/w wwwwwwww addr f40h uart data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value -------------------- --------------------- ---------------------- ----------------- -------------- =
ps022815-0206 uart z8 encore! xp ? 4k series product specification 101 txd?transmit data uart transmitter data byte to be shifted out through the txd x pin. uart receive data register data bytes received through the rxd x pin are stored in the uart receive data (uxrxd) register ( table 63 ). the read-only uart receive data register shares a regis- ter file address with the write-only uart transmit data register. rxd?receive data uart receiver data byte from the rxd x pin uart status 0 register the uart status 0 (uxstat0) and status 1(uxstat1) registers ( tables 64 and 65 ) iden- tify the current uart operatin g configuration and status. rda?receive data available this bit indicates that the uart receive data register has received data. reading the uart receive data register clears this bit. 0 = the uart receive data register is empty. 1 = there is a byte in the uart receive data register. pe?parity error this bit indicates that a parity error has occurred. reading the uart receive data regis- ter clears this bit. table 63. uart receive data register (u0rxd) bits 7 6 5 4 3 2 1 0 field rxd reset xxxxxxxx r/w rrrrrrrr addr f40h table 64. uart status 0 register (u0stat0) bits 7 6 5 4 3 2 1 0 field rda pe oe fe brkd tdre txe cts reset 000001 1 x r/w rrrrrr r r addr f41h
ps022815-0206 uart z8 encore! xp ? 4k series product specification 102 0 = no parity error has occurred. 1 = a parity error has occurred. oe?overrun error this bit indicates that an overrun error has o ccurred. an overrun occurs when new data is received and the uart receive data register has not been read. if the rda bit is reset to 0, reading the uart receive da ta register clears this bit. 0 = no overrun error occurred. 1 = an overrun error occurred. fe?framing error this bit indicates that a framing error (no st op bit following data reception) was detected. reading the uart receive data register clears this bit. 0 = no framing error occurred. 1 = a framing error occurred. brkd?break detect this bit indicates that a break occurred. if the data bits, parity/multip rocessor bit, and stop bit(s) are all 0s this bit is set to 1. readin g the uart receive data register clears this bit. 0 = no break occurred. 1 = a break occurred. tdre?transmitter data register empty this bit indicates that the uart transmit data register is empty and ready for additional data. writing to the uart transmit data register resets this bit. 0 = do not write to the uart transmit data register. 1 = the uart transmit data register is ready to receive an additional byte to be transmit- ted. txe?transmitter empty this bit indicates that the transmit shift regist er is empty and character transmission is fin- ished. 0 = data is currently transmitting. 1 = transmission is complete. cts?cts signal when this bit is read it re turns the level of the cts signal. this signal is active low.
ps022815-0206 uart z8 encore! xp ? 4k series product specification 103 uart status 1 register this register contains multipro cessor control and status bits. reserved?must be 0. newfrm?status bit denoting the start of a new frame. reading the uart receive data register resets this bit to 0. 0 = the current byte is not the first data byte of a new frame. 1 = the current byte is the fi rst data byte of a new frame. mprx?multiprocessor receive returns the value of the most recent multip rocessor bit received. reading from the uart receive data register resets this bit to 0. uart control 0 and co ntrol 1 registers the uart control 0 (uxctl0) and control 1 (uxctl1) registers ( tables 66 and 67 ) configure the properties of the uart?s tran smit and receive operations. the uart con- trol registers must not be writ ten while the uart is enabled. ten?transmit enable this bit enables or di sables the transmitter. the enable is also controlled by the cts signal and the ctse bit. if the cts signal is low and the ctse bit is 1, the transmitter is enabled. 0 = transmitter disabled. 1 = transmitter enabled. table 65. uart status 1 register (u0stat1) bits 7 6 5 4 3 2 1 0 field reserved newfrm mprx reset 000000 0 0 r/w rrrrr/wr/wr r addr f44h table 66. uart control 0 register (u0ctl0) bits 7 6 5 4 3 2 1 0 field ten ren ctse pen psel sbrk stop lben reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f42h
ps022815-0206 uart z8 encore! xp ? 4k series product specification 104 ren?receive enable this bit enables or disables the receiver. 0 = receiver disabled. 1 = receiver enabled. ctse?cts enable 0 = the cts signal has no effect on the transmitter. 1 = the uart recognizes the cts signal as an enable control from the transmitter. pen?parity enable this bit enables or disables parity. even or odd is determined by the psel bit. 0 = parity is disabled. 1 = the transmitter sends data with an additio nal parity bit and the receiver receives an additional parity bit. psel?parity select 0 = even parity is transmitted an d expected on all received data. 1 = odd parity is transmitted an d expected on all received data. sbrk?send break this bit pauses or breaks data transmission. sending a break interrupts any transmission in progress, so ensure that the transmitter has finished sending da ta before setting this bit. 0 = no break is sent. 1 = forces a break condition by setting th e output of the transmitter to zero. stop?stop bit select 0 = the transmitter sends one stop bit. 1 = the transmitter sends two stop bits. lben?loop back enable 0 = normal operation. 1 = all transmitted data is looped back to the receiver. mpmd[1:0]?multip rocessor mode if multiprocessor (9-b it) mode is enabled, 00 = the uart generates an interrupt requ est on all received bytes (data and address). 01 = the uart generates an interrupt request only on received address bytes. 10 = the uart generates an interrupt reques t when a received address byte matches the value stored in the address compare register and on all successive data bytes until an table 67. uart control 1 register (u0ctl1) bits 7 6 5 4 3 2 1 0 field mpmd[1] mpen mpmd[0] mpbt depol brgctl rdairq iren reset 000000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f43h
ps022815-0206 uart z8 encore! xp ? 4k series product specification 105 address mismatch occurs. 11 = the uart generates an interrupt reques t on all received data bytes for which the most recent address byte matched the value in the address compare register. mpen?multiprocessor (9-bit) enable this bit is used to enable multiprocessor (9-bit) mode. 0 = disable multiprocessor (9-bit) mode. 1 = enable multiproce ssor (9-bit) mode. mpbt?multiprocessor bit transmit this bit is applicable only when multiproc essor (9-bit) mode is enabled. the 9th bit is used by the receiving device to determine if the data byte co ntains address or data infor- mation. 0 = send a 0 in the multipro cessor bit location of the data stream (data byte). 1 = send a 1 in the multipro cessor bit location of the data stream (address byte). depol?driver enable polarity 0 = de signal is active high. 1 = de signal is active low. brgctl?baud rate control this bit causes an alternate uart behavior de pending on the value of the ren bit in the uart control 0 register. when the uart receiver is not enabled (ren=0), this bit determines whether the baud rate generator issues interrupts. 0 = reads from the baud rate high and low byte registers return the brg reload value 1 = the baud rate generator generates a receive interrupt when it counts down to 0. reads from the baud rate high and low byte registers return the current brg count value. when the uart receiver is enabled (ren=1), this bit allows reads from the baud rate registers to return the brg count value instead of the reload value. 0 = reads from the baud rate high and low byte registers return the brg reload value. 1 = reads from the baud rate high and low by te registers return the current brg count value. unlike the timers, there is no mechan ism to latch the low byte when the high byte is read. rdairq ?receive data interrupt enable 0 = received data and receiver errors generat es an interrupt request to the interrupt con- troller. 1 = received data does not generate an interrupt request to the interrupt controller. only receiver errors generate an interrupt request. iren?infrared encoder/decoder enable 0 = infrared encoder/decoder is di sabled. uart operates normally. 1 = infrared encoder/decoder is enabled. the uart transmits and r eceives data through the infrared en coder/decoder.
ps022815-0206 uart z8 encore! xp ? 4k series product specification 106 uart address compare register the uart address compare (u xaddr) register stores th e multi-node network address of the uart (see table 68 ). when the mpmd[1] bit of uart control register 0 is set, all incoming address bytes are compared to th e value stored in the address compare reg- ister. receive interrupts and rda assertions only occur in the event of a match. comp_addr?compare address this 8-bit value is compared to incoming address bytes. uart baud rate high and low byte registers the uart baud rate hi gh (uxbrh) and low byte (uxbrl) registers ( tables 69 and 70 ) combine to create a 16-bit baud rate diviso r value (brg[15:0]) that sets the data trans- mission rate (baud rate) of the uart. table 68. uart address co mpare register (u0addr) bits 7 6 5 4 3 2 1 0 field comp_addr reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f45h table 69. uart baud rate high byte register (u0brh) bits 7 6 5 4 3 2 1 0 field brh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f46h table 70. uart baud rate low byte register (u0brl) bits 7 6 5 4 3 2 1 0 field brl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f47h
ps022815-0206 uart z8 encore! xp ? 4k series product specification 107 the uart data rate is calcula ted using the following equation: for a given uart data rate, calcu late the integer baud rate di visor value using the follow- ing equation: the baud rate error relative to the acceptable baud rate is calculated usin g the following equation: for reliable communication, the uart baud ra te error must never exceed 5 percent. table 71 provides information about data rate e rrors for popular baud rates and commonly used crystal osc illator frequencies. table 71. uart baud rates 10.0 mhz system clock 5 .5296 mhz system clock acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 1 625.0 0.00 625.0 n/a n/a n/a 250.0 3 208.33 -16.67 250.0 1 345.6 38.24 115.2 5 125.0 8.51 115.2 3 115.2 0.00 57.6 11 56.8 -1.36 57.6 6 57.6 0.00 38.4 16 39.1 1.73 38.4 9 38.4 0.00 19.2 33 18.9 0.16 19.2 18 19.2 0.00 9.60 65 9.62 0.16 9.60 36 9.60 0.00 4.80 130 4.81 0.16 4.80 72 4.80 0.00 2.40 260 2.40 -0.03 2.40 144 2.40 0.00 1.20 521 1.20 -0.03 1.20 288 1.20 0.00 0.60 1042 0.60 -0.03 0.60 576 0.60 0.00 0.30 2083 0.30 0.2 0.30 1152 0.30 0.00 uart baud rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ------------------- --------------------- --------------------- ------------------ --------------- = uart baud rate divisor value (brg) round system clock frequency (hz) 16 uart data rate (bits/s) -------------------- --------------------- ---------------------- ------------- ?? ?? = uart baud rate error (%) 100 actual data rate desired data rate ? desired data rate ------------------- --------------------- --------------------- ------------------ ----------------- - ?? ?? =
ps022815-0206 uart z8 encore! xp ? 4k series product specification 108 3.579545 mhz system clock 1.8432 mhz system clock acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) 1250.0 n/a n/a n/a 1250.0 n/a n/a n/a 625.0 n/a n/a n/a 625.0 n/a n/a n/a 250.0 1 223.72 -10.51 250.0 n/a n/a n/a 115.2 2 111.9 -2.90 115.2 1 115.2 0.00 57.6 4 55.9 -2.90 57.6 2 57.6 0.00 38.4 6 37.3 -2.90 38.4 3 38.4 0.00 19.2 12 18.6 -2.90 19.2 6 19.2 0.00 9.60 23 9.73 1.32 9.60 12 9.60 0.00 4.80 47 4.76 -0.83 4.80 24 4.80 0.00 2.40 93 2.41 0.23 2.40 48 2.40 0.00 1.20 186 1.20 0.23 1.20 96 1.20 0.00 0.60 373 0.60 -0.04 0.60 192 0.60 0.00 0.30 746 0.30 -0.04 0.30 384 0.30 0.00 table 71. uart baud rates (continued)
ps022815-0206 infrared encoder/decoder z8 encore! xp ? 4k series product specification 109 infrared encoder/decoder overview the z8 encore! xp ? 4k series products contain a fu lly-functional, high-performance uart to infrared encoder/decode r (endec). the infrared endec is integrated with an on- chip uart to allow easy co mmunication between the z8 encore! and irda physical layer specification, version 1.3-compliant infrared transceivers. infrared communication provides secure, reliable, low-cost, point-t o-point communication between pcs, pdas, cell phones, printers and other infrared enabled devices. architecture figure 16 illustrates the architectur e of the infrared endec. figure 16.infrared data comm unication system block diagram operation when the infrared endec is en abled, the transmit data from the associated on-chip uart is encoded as digital signals in accordance with the irda standard and output to the infra- red transceiver through the txd pin. likewise, data received from the infrared transceiver interrupt signal rxd txd infrared encoder/decoder uart rxd txd system clock i/o address data infrared transceiver rxd txd baud rate clock (endec)
ps022815-0206 infrared encoder/decoder z8 encore! xp ? 4k series product specification 110 is passed to the infrared endec through the rx d pin, decoded by the infrared endec, and passed to the uart. communication is hal f-duplex, which means simultaneous data transmission and reception is not allowed. the baud rate is set by the uart?s baud rate generator and supports irda standard baud rates from 9600 baud to 115.2 kbaud. higher baud rates are possible, but do not meet irda specifications. the uart must be enable d to use the infrared endec. the infrared endec data rate is calculated using the following equation: : transmitting irda data the data to be transmitted using the infrared transceiver is first se nt to the uart. the uart?s transmit signal (txd) and baud rate clock are used by the irda to generate the modulation signal (ir_txd) that drives th e infrared transceiver. each uart/infrared data bit is 16 clocks wide. if the data to be transmitted is 1, the ir_txd signal remains low for the full 16 clock period. if the data to be transmitted is 0, the transmitter first out- puts a 7 clock low period, followed by a 3 clock high pulse. finally, a 6 clock low pulse is output to complete the fu ll 16 clock data period. figure 17 illustrates irda data transmis- sion. when the infrared endec is enabled, th e uart?s txd signal is internal to the z8 encore! xp ? 4k series products while the ir_txd signal is output through the txd pin. figure 17.infrared data transmission infrared data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ------------------- --------------------- --------------------- ------------------ --------------- = baud rate ir_txd uart?s 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 7-clock delay 3 clock pulse txd clock
ps022815-0206 infrared encoder/decoder z8 encore! xp ? 4k series product specification 111 receiving irda data data received from the infrare d transceiver using the ir_rxd signal through the rxd pin is decoded by the infrared endec and passed to the uart. the uart?s baud rate clock is used by the infrared endec to generate th e demodulated signal (rxd) that drives the uart. each uart/infrared da ta bit is 16-clocks wide. figure 18 illustrates data recep- tion. when the infrared endec is enabled, the uart?s rxd sign al is internal to the z8 encore! xp ? 4k series products while the ir_rxd signal is received through the rxd pin. figure 18.irda data reception infrared data reception the system clock frequency must be at least 1.0 mhz to ensure proper reception of the 1.4 s minimum width pulses allowed by the irda standard. endec receiver synchronization the irda receiver uses a local baud rate clock co unter (0 to 15 clock periods) to generate an input stream for the uart and to create a sampling window for detection of incoming pulses. the generated uart input (uart rxd) is delayed by 8 baud rate clock periods with respect to the incoming irda data stream. when a fa lling edge in the input data stream is detected, the endec counter is rese t. when the count reac hes a value of 8, the uart rxd value is updated to reflect the va lue of the decoded data. when the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. the window remains open until th e count again reaches 8 (in other words, 24 baud clock periods since the previous pulse was detect ed), giving the endec a sampling window of baud rate uart?s ir_rxd 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 8 clock delay clock rxd 16 clock period 16 clock period 16 clock period 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 min. 1.4 s pulse caution:
ps022815-0206 infrared encoder/decoder z8 encore! xp ? 4k series product specification 112 minus four baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse. if an incoming pulse is dete cted inside this window this process is repeated. if the incoming data is a logical 1 (n o pulse), the endec returns to the initial state and waits for the next falling edge. as eac h falling edge is detected, the endec clock counter is reset, resynchronizing the endec to the incoming signal, allowing the endec to tolerate jitter and baud rate e rrors in the incoming datastre am. resynchronizing the endec does not alter the operation of the uart, which ultimately re ceives the data. the uart is only synchronized to the incoming data stream when a start bit is received. infrared encoder/decoder c ontrol register definitions all infrared endec configuration and status information is set by the uart control regis- ters as defined beginning on page 89 . to prevent spurious signals during irda da ta transmission, set the iren bit in the uart control 1 register to 1 to en able the infrared encoder/decoder before enabling the gpio port alternate func tion for the corresponding pin. caution:
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 113 analog-to-digital converter overview the analog-to-digital converter (adc) converts an analog input signal to its digital repre- sentation. the features of th is sigma-delta adc include: ? 11-bit resolution in differential mode ? 10-bit resolution in single-ended mode ? eight single-ended analog input sources ar e multiplexed with general-purpose i/o ports ? 9th analog input obtained from temperature sensor peripheral ? 11 pairs of differential inputs also mu ltiplexed with general-purpose i/o ports ? low-power operational amplifier (lpo) ? interrupt on conversion complete ? interrupt on sample value greater than programmable high threshold ? interrupt on sample value smalle r than programmable low threshold ? bandgap generated internal voltage re ference with two selectable levels ? manual in-circuit calibration is possible employing user code (offset calibration) ? factory calibrated for in-circuit error compensation architecture figure 19 illustrates the major functional blocks of the adc. an analog multiplexer net- work selects the adc inpu t from the available analog pins, ana0 through ana7. the input stage of the adc allows both di fferential gain and buffering. the following input options are available: ? unbuffered input (single-en ded and differential modes) ? buffered input with unity gain (s ingle-ended and differential modes) ? lpo output with full pin a ccess to the feedback path
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 114 figure 19.analog-to-digital converter block diagram operation data format in both single-ended and differential modes, the effective output of the adc is an 11- bit, signed, two?s complement dig ital value. in differential mode, the adc temp analog input multiplexer internal voltage reference generator analog in + ref input sensor analog in - + - vref pin adc irq adc data 13 bit sigma-delta adc vrefsel 2 13 analog input multiplexer ana7 ana6 ana5 ana4 ana3 ana2 ana1 ana0 ana5 ana4 ana3 ana2 ana1 ana0 for offset calibration anain 4 buffer amplifier + - low-power operational amplifier buffmode vrefext amplifier tristates when disabled
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 115 can output values across the entire 11-b it range, from -1024 to +1023. in single- ended mode, the output generally ranges from 0 to +1023, but offset errors can cause small negative values. the adc registers actually return 13 bits of data, but the two lsbs are intended for com- pensation use only. when the software compensation routine is performed on the 13 bit raw adc value, two bits of reso lution are lost because of a rounding error. as a result, the final value is an 11- bit number. automatic powerdown if the adc is idle (no conversions in progre ss) for 160 consecutive system clock cycles, portions of the adc are automatically powe red down. from this powerdown state, the adc requires 40 system clock cycles to powe r up. the adc powers up when a conver- sion is requested by the adc control register. single-shot conversion when configured for single-shot conversion, the adc performs a single analog-to-digital conversion on the selected analog input chan nel. after completion of the conversion, the adc shuts down. the steps for setting up th e adc and initiating a single-shot conversion are as follows: 1. enable the desired analog inputs by configuring the general-purpose i/o pins for alternate analog function. this configura tion disables the digital input and output drivers. 2. write the adc high threshold register and adc low threshold register if the alarm function is required. 3. write the adc control/status register 1 to configure the adc ? write to bufmode[2:0] to select single-ended or differential mode, as well as unbuffered or buffered mode. ? if the alarm function is required, set almhen and/or almlen. ? write the refselh bit of the pair { refselh , refsell } to select the internal voltage reference level or to disa ble the internal reference. the refsell bit is. contained in the adc control register 0 . 4. write to the adc control register 0 to configure the adc and begin the conversion. the bit fields in the adc control regist er can be written simultaneously (the adc can be configured and enabled w ith the same write instruction): ? write to the anain[3:0] field to select from the available analog input sources (different input pins available depending on the device) ? clear cont to 0 to select a single-shot conversion.
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 116 ? if the internal voltage reference mu st be output to a pin, set the refext bit to 1. the internal voltage reference must be enabled in this case. ? write the refsell bit of the pair { refselh , refsell } to select the internal voltage reference level or to disa ble the internal reference. the refselh bit is contained in the adc control/status register 1 . ? set cen to 1 to start the conversion. 5. cen remains 1 while the conversion is in progress. a single-shot conversion requires 5129 system clock cycles to complete. if a single-shot conversion is requested from an adc powered-down state, the adc uses 40 additional clock cycles to power up before beginning the 5129 cycle conversion. 6. when the conversion is complete, the adc control logic performs the following operations: ? 13-bit two?s-complement result writte n to {adcd_h[7:0], adcd_l[7:3]}. ? cen resets to 0 to indicate the conversion is complete. ? if the high and low alarms are disabled, an interrupt request is sent to the interrupt controller deno ting conversion complete. ? if the high alarm is enabled and the adc va lue is higher than the alarm threshold, an interrupt is generated. ? if the low alarm is enabled and the adc va lue is lower than the alarm threshold, an interrupt is generated. 7. if the adc remains idle for 160 consecutive system clock cycles, it is automatically powered-down. continuous conversion when configured for continuous conversion , the adc continuously performs an analog- to-digital conversion on the sel ected analog input. each new data value over-writes the previous value stored in the adc data register s. an interrupt is generated after each con- version. in continuous mode, adc updates are limited by the input signal bandwidth of the adc and the latency of the adc and its digital filter. step changes at the input are not immediately detected at the next output fro m the adc. the response of the adc (in all modes) is limited by the input signal bandwidth and the latency. follow these steps for setting up the adc and initiating continuous conversion: 1. enable the desired analog input by configuring the general-purpose i/o pins for alternate function. this action disables the digital input and output driver. 2. write the adc high threshold register and adc low threshold register if the alarm function is required. caution:
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 117 3. write the adc control/status register 1 to configure the adc ? write to bufmode [2:0] to select single-ended or differential mode, as well as unbuffered or buffered mode. ? if the alarm function is required, set almhen and/or almlen. ? write the refselh bit of the pair { refselh , refsell } to select the internal voltage reference level or to disa ble the internal reference. the refsell bit is contained in the adc control register 0 . 4. write to the adc control register 0 to configure the adc fo r continuous conversion. the bit fields in the adc control re gister may be written simultaneously: ? write to the anain[3:0] field to select from the available analog input sources (different input pins available depending on the device) ? set cont to 1 to select continuous conversion. ? if the internal vref must be output to a pin, set the refext bit to 1. the internal voltage reference must be enabled in this case. ? write the refsell bit of the pair { refselh, refsell } to select the internal voltage reference level or to disa ble the internal reference. the refselh bit is contained in adc control/status register 1 . ? set cen to 1 to start the conversions. 5. when the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for powe r-up, if necessary), the adc control logic performs the following operations: ? cen resets to 0 to indicate the first conversion is complete. cen remains 0 for all subsequent conversions in continuous operation. ? an interrupt request is sent to the interrupt controller to indicate the conversion is complete. 6. the adc writes a new data result every 256 system clock cycles. for each completed conversion, the adc control logic performs the following operations: ? writes the 13-bit two?s complement r esult to {adcd_h[7:0], adcd_l[7:3]}. ? if the high and low alarms are disabled, sen ds an interrupt request to the interrupt controller denoting conversion complete. ? if the high alarm is enabled and the adc va lue is higher than the alarm threshold, generates an interrupt. ? if the low alarm is enabled and the adc va lue is lower than th e alarm threshold, generates an interrupt. 7. to disable continuous conversion, clear the cont bit in the adc control register to 0.
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 118 programmable trigger point alarm the adc contains two programmable trigger values, defined in the adc high threshold (adcthh) register ( table 76 on page 128 ) and the adc low threshold (adctlh) register ( table 77 on page 128 ). each of these values is 8 bits and is not a two?s com- plement number. the alarm is intended for si ngle-ended operation and so the alarm values reflect positive numbers only. both thresholds have independent control and status bits. when the adc is enabled and the adc value exceeds the high threshold, an adc inter- rupt is asserted and the high threshold status bit is set. when enabled and the adc value is less than the low threshold, an adc interrupt is asserted and the low threshold status bit is set. because the alarm value is positive it is compared to the most significant 8 data bits of the adc value, excluding the sign bit. th e adc alarm bits are compared to { adcd_h[6:0],adcd_l[7] }. alternatively, the alarm va lue is compared to the adc value shifted left by one bit. negative adc va lues never trigger the high alarm and always trigger the low alarm. because the adc output is software compensated for offset, nega- tive (pre-compensated) values can occur in single-ended mode. the alarm is primarily intended for use in continuous mode so that the cpu can determine threshold crossings w ithout servicing interrupts for all adc samples. if used in single-shot mode, the adc will only interrupt the cpu if the single sample triggers an alarm. the alarm status bits are updated on each co nversion, regardless of the alarm enable bit values. the alarm enable bits only determine whether or no t an interrupt is generated. interrupts the adc is able to interrupt the cpu under three conditions: ? when a conversion has been completed ? when the 8 most significant bits of a sa mple exceed the programmable high threshold adcthh[7:0] ? when the 8 most significant bits of a sample is less than the pr ogrammable low threshold adctlh[7:0] the conversion interrupt occurs when the adc is enabled and both alarms are disabled. when either or both alarms are enabled, the conversion interrupt is disabled and only the alarm interrupts may occur. when the adc is disabled, none of the three so urces can cause an interrupt to be asserted; however, an interrupt pending when th e adc is disabled is not cleared. the three interrupt events share a common cpu interrupt. the interrupt service routine must query the adc control/status (adcctl1 ) register to determine the cause of an
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 119 adc interrupt. the register bits denoting adc alarm status can only be set by hardware and are cleared by writing a 1. calibration and compensation the z8 encore! xp ? 4k series adc is factory calibrated for offset error and gain error, with the compensation data stored in flash me mory. alternatively, us ers can perform their own calibration, storing the values into flash themselves. thirdly, the user code can per- form a manual offset calibration during differential mode operation. factory calibration devices that have been factory calibrated cont ain 30 bytes of calibration data in the flash option bit space. this data cons ists of 3 bytes for each inpu t mode, one for offset and two for gain correction. see zilog calibration data on page 155 for a list of input modes for which calibration data exists. user calibration if the user has precision references available, its own external calibration can be per- formed using any input modes. this calibration data will take into account buffer offset and non-linearity, so it is recommended that this calibration be performed separately for each of the adc input modes planned for use. manual offset calibration when uncalibrated, the adc has significant offset (see table 138, analog-to-digital con- verter electrical characteristics and timing, on page 221 for details). subsequently, man- ual offset calibration capability is built into the block. when the adc control register 0 sets the input mode ( anain[2:0] ) to manual offset calibration mode, the differential inputs to the adc are shorted to gether by an internal switch. reading the adc value at this point produces 0 in an id eal system. the value actually read is the adc offset. this value can be stor ed in non-volatile memory ( non-volatile data storage on page 163 ) and accessed by user code to comp ensate for the input offset error. there is no provision for manual gain calibration. software compensation procedure using factory calibration data overview. the value read from the adc high an d low byte registers is uncompen- sated. the user mode software must apply gain and offset correction to this uncom- pensated value for maximum accuracy. the following form ula yields the compensated value: adc comp = (adc uncomp - offcal) + ((adc uncomp - offcal)*gaincal)/2 16
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 120 where gaincal is the gain calibration value, offcal is the offs et calibration value and adc uncomp is the uncompensated value read from the adc. all values are in two?s complement format. the offset compensation is performed first, followed by the gain compensation. one bit of resolution is lost because of rounding on both the offset and gain computations. as a result the adc registers read back 13 b its: 1 sign bit, two ca libration bits lost to rounding and 10 data bits. also note that in the second term, the multip lication should be performed before the division by 2 16 . otherwise, the the second term w ill incorrectly eval uate to zero. although the adc can be used without the gain and offset compensation, it does exhibit non-unity gain. designing the adc with su b-unity gain reduces noise across the adc range but requires the adc results to be scaled by a factor of 8/7. adc compensation details high efficiency assembly code that performs this compensation is av ailable for download on www.zilog.com. the following is a bit-sp ecific description of the adc compensation process used by this code. the following data bit definitions are used: 0-9, a-f = bit indices in hexadecimal s = sign bit v = overflow bit - = unused input data: msb lsb s b a 9 8 7 6 5 4 3 2 1 0 - - v (adc) adc output word; if v = 1, the data is invalid s 6 5 4 3 2 1 0 offset correction byte s s s s s 7 6 5 4 3 2 1 0 0 0 0 (offset) offset byte shifted to align with adc data s e d c b a 9 8 7 6 5 4 3 2 1 0 (gain) gain correction word note: caution:
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 121 compensation steps: 1. correct for offset adc msb adc lsb - offset msb offset lsb = #1 msb #1 lsb 2. take absolute value of the offset corrected adc value if negative ? the gain correction factor is computed assuming positive numb ers, with sign restoration afterward. #2 msb #2 lsb also take absolute value of the gain correction word if negative . again msb again lsb 3. multiply by gain correction word. if in differential mode, there are two gain correction values: one for positive adc va lues, another for negative adc values. based on the sign of #2, use the appropriate gain correction word. #2 msb #2 lsb * again msb again lsb = #3 #3 #3 #3 4. round the result and discard the least sign ificant two bytes (this is equivalent to dividing by 2 16 ). #3 #3 #3 #3 - 0x00 0x00 0x80 0x00 = #4 msb #4 lsb 5. determine sign of the gain correction fact or using the sign bits from step #2. if the offset corrected adc value and the gain correction word have the same sign, then the factor is positive and is left unchanged. if they have differing signs, then the factor is negative and should be multiplied by -1. #5 msb #5 lsb
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 122 6. add the gain correction factor to the original offset corrected value. #5 msb #5 lsb + #1 msb #1 lsb = #6 msb #6 lsb 7. shift the result to the right, using the sign bit de termined in step #1 above. this will allow for the detection of computational overflow. s-> #6 msb #6 lsb output data the following is the output form at of the corrected adc value. msb lsb s v b a 9 8 7 6 5 4 3 2 1 0 - - the overflow bit in the corrected output in dicates that the computed value was greater than the maximum logical valu e (+1023) or less than the minimum logical value (-1024). unlike the hardware overflow b it, this is not a simple binary flag. for a normal sample (non-overflow), the sign and the overflow bit will match. if the sign bit and overflow bit do not match, a computational overflow has occurred. input buffer stage many applications require the measurement of an input voltage source with a high output impedance. this adc provides a buffered inpu t for such situations. the drawback of the buffered input is a limitation of the input rang e. when using unity gain buffered mode, the input signal must be prevented from coming too close to either v ss or v dd . see table 138, analog-to-digital converter el ectrical characteristics and timing, on page 221 for details. this condition applie s only to the input voltage level (w ith respect to ground) of each dif- ferential input signal. the actual differential input voltage magnitude may be less than 300 mv. the input range of the unbuffered adc swings from v ss to v dd . input signals smaller than 300 mv must use the unbuffered input mode. if these signals do not contain low out- put impedances, they might require off-chip buffering.
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 123 signals outside the allowable input range can be used without instability or device dam- age. any adc readings made outside the input range are su bject to greater inaccuracy than specified. low-power operational amplifier (lpo) the lpo is a general-purpose ope rational amplifier. each of the three ports of the ampli- fier is accessible from the package pins. the lpo contains only one pin configuration: ana0 is the output/feedback node, ana1 is the inverting input and ana2 is the non- inverting input. to use the lpo, it must be enabled in the power control register 0 (pwrctl0) . the default state of the lpo is off. to use the lpo, the lpo bit must be cleared, turning it on ( power control register 0 (pwrctl0) on page 31 ). when making normal adc measurements on ana0 (measurements not invo lving the lpo output), the lpo bit must be off. turning the lpo bit on interferes wi th normal adc measurements. finally, this bit enables the amplifier even in stop mode. if the amplifie r is not required in stop mode, disable it. failing to perfo rm this results in stop mode currents greater than speci- fied. as with other adc measurements, any pins u sed for analog purposes must be configured as such in the gpio registers (see port a?d alternate function sub-registers on page 42 ). lpo output measurements are made on ana0, as selected by the anain[3:0] bits of adc control register 0 . it is also possible to make single-ended measurements on ana1 and ana2 while the amplifier is enabled, whic h is often useful for determining offset con- ditions. differential measurements between ana0 and ana2 may be useful for noise cancellation purposes. if the lpo output is routed to the adc, then the buffmode [2:0] bits of adc control/sta- tus register 1 must also be configured for unity-gai n buffered operation. using the lpo in an unbuffered mode is not recommended. when either input is overdriv en, the amplifier output satura tes at the positive or negative supply voltage. no instability results.
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 124 adc control register definitions adc control register 0 the adc control register 0 (adcctl0) sel ects the analog input channel and initiates the analog-to-digital conversion. it also se lects the voltage refe rence configuration. cen?conversion enable 0 = conversion is complete. writing a 0 produc es no effect. the adc automatically clears this bit to 0 when a co nversion is complete. 1 = begin conversion. writing a 1 to this bit st arts a conversion. if a conversion is already in progress, the conversion restarts. this bit remains 1 until the conversion is complete. refsell?voltage reference level select low bit; in conjunction with the high bit (refselh) in adc control/status register 1 , this determines the level of the internal voltage reference; the following details the effects of {refselh, refsell}; note that this reference is independent of the comparator reference 00= internal reference disabled, reference comes from external pin 01= internal refere nce set to 1.0 v 10= internal reference set to 2.0 v (default) 11= reserved refout - internal reference output enable 0 = reference buffer is disabled; vref pin is available for gpio or analog functions 1 = the internal adc reference is buff ered and driven out to the vref pin when the adc is used with an extern al reference ({refselh,refsell}=00), the refout bit must be set to 0. cont 0 = single-shot conversion. adc data is output once at completion of the 5129 system clock cycles (measurements of the internal temperature sensor take twice as long) 1 = continuous conversion. adc data updated every 256 system clock cycles after an ini- tial 5129 clock conversion (measurements of th e internal temperature sensor take twice as long) table 72. adc control register 0 (adcctl0) bits 7 6 5 4 3 2 1 0 field cen refsell refout cont anain[3:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f70h warning:
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 125 anain[3:0]?analog input select these bits select the analog inpu t for conversion. not all port pins in this list are available in all packages for the z8 encore! xp ? 4k series. refer to the chapter pin description on page 7 for information regarding the port pins available with each package style. do not enable unavailable analog in puts. usage of these bits changes depending on the buffer mode selected in adc control/status register 1 . for the reserved values, all inpu t switches are disabled to avoid leakage or other undesir- able operation. adc samples taken with reserved bit settings are undefined. single-ended: 0000 = ana0 (transimpedance amp output when enabled) 0001 = ana1 (transimpedance amp inverting input) 0010 = ana2 (transimpedance amp non-inverting input) 0011 = ana3 0100 = ana4 0101 = ana5 0110 = ana6 0111 = ana7 1000 = reserved 1001 = reserved 1010 = reserved 1011 = reserved 1100 = hold transimpedance input nodes (ana1 and ana2) to ground. 1101 = reserved 1110 = temperature sensor. 1111 = reserved. differential (non-inverting input an d inverting input respectively): 0000 = ana0 and ana1 0001 = ana2 and ana3 0010 = ana4 and ana5 0011 = ana1 and ana0 0100 = ana3 and ana2 0101 = ana5 and ana4 0110 = ana6 and ana5 0111 = ana0 and ana2 1000 = ana0 and ana3 1001 = ana0 and ana4 1010 = ana0 and ana5 1011 = reserved 1100 = reserved 1101 = reserved 1110 = reserved 1111 = manual offset calibration mode
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 126 adc control/status register 1 the adc control/statu s register 1 (adcctl1) configures the input buffer stage, enables the threshold interrupts an d contains the status of both threshold triggers. it is also used to select the voltage reference configuration. refselh?voltage reference le vel select high bit; in co njunction with the low bit (refsell) in adc control register 0 , this determines the leve l of the internal voltage reference; the following details the effe cts of {refselh, refsell}; this reference is independent of the comparator reference 00= internal reference disabled, reference comes from external pin 01= internal refere nce set to 1.0 v 10= internal reference set to 2.0 v (default) 11= reserved almhst?alarm high status; this bit can only be set by hardware and must be written with a 1 to clear 0= no alarm occurred. 1= a high threshold alarm occurred. almlst?alarm low status; this bit can only be set by hardware and must be written with a 1 to clear 0= no alarm occurred. 1= a low threshold alarm occurred. almhen?alarm high enable 0= alarm interrupt for high threshold is disab led. the alarm status bit remains set when the alarm threshold is passed. 1= high threshold alar m interrupt is enabled. almlen?alarm low enable 0= alarm interrupt for low threshold is disable d. the alarm status bit remains set when the alarm threshold is passed. 1= low threshold alarm interrupt is enabled. bufmode[2:0] - input buffer mode select 000 = single-ended, unbuffered input 001 = single-ended, buffered input with unity gain table 73. adc control/status register 1 (adcctl1) bits 7 6 5 4 3 2 1 0 field refselh almhst almlst almhen almlen bufmode[2:0] reset 10000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f71h
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 127 010 = reserved 011 = reserved 100 = differential, unbuffered input 101 = differential, buffer ed input with unity gain 110 = reserved 111 = reserved adc data high byte register the adc data high byte (adcd_h) register contains the upper eight bits of the adc output. the output is an 13-bit two?s compleme nt value. during a single-shot conversion, this value is invalid. access to the adc data hi gh byte register is read-only. reading the adc data high byte regi ster latches data in th e adc low bits register. adcdh?adc data high byte this byte contains the upper eight bits of th e adc output. these bits are not valid during a single-shot conversion. during a continuous conversion, the most recent conversion out- put is held in this register. the se bits are undefined after a reset. adc data low bits register the adc data low byte (adcd_l) register c ontains the lower bits of the adc output as well as an overflow status bit. the output is a 13-bit two?s complement value. during a single-shot conversion, this valu e is invalid. access to the ad c data low byte register is read-only. reading the adc data high byte register latches data in the adc low bits register. table 74. adc data high byte register (adcd_h) bits 7 6 5 4 3 2 1 0 field adcdh reset xxxxxxxx r/w rrrrrrrr addr f72h table 75. adc data low bits register (adcd_l) bits 7 6 5 4 3 2 1 0 field adcdl reserved ovf reset xxxxxxxx r/w rrrrrrrr addr f73h
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 128 adcdl?adc data low bits these bits are the least significant five bits of the 13-bits of the adc output. these bits are undefined after a reset. reserved?must be undefined. ovf?overflow status 0= a hardware overflow did not occu r in the adc for the current sample. 1= a hardware overflow did occur in the ad c for the current sample, therefore the cur- rent sample is invalid. adc high threshold register the adc high threshold (adcthh) register is used to set the trigger point above which an adc sample causes a cpu interrupt. adcthh?adc high threshold these bits are compared to the most signific ant 8 bits of the single-ended adc value. if the adc value exceeds this, an interrupt is asse rted. the alarm function is not available in differential mode. adc low threshold register the adc low threshold (adctlh) register is used to set the trig ger point below which an adc sample causes a cpu interrupt. adctlh?adc low threshold these bits are compared to the most signific ant 8 bits of the single-ended adc value. if table 76. adc high thre shold high byte (adcthh) bits 7 6 5 4 3 2 1 0 field adcthh reset ff r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f74h table 77. adc low thresho ld high byte (adctlh) bits 7 6 5 4 3 2 1 0 field adctlh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f76h
ps022815-0206 analog-to-digital converter z8 encore! xp ? 4k series product specification 129 the adc value drops below this value an inte rrupt is asserted. the alarm function is not available in differential mode.
ps022815-0206 comparator z8 encore! xp ? 4k series product specification 130 comparator overview the z8 encore! xp ? 4k series devices feature a general purpose comparator that com- pares two analog input signals. these analog signals may be external stimulus from a pin (cinp and/or cinn) or internally generated signals. both a progra mmable voltage refer- ence and the temperature sensor output voltage are available internally. the output is available as an interrupt source or can be routed to an external pin. figure 20.compara tor block diagram operation when the positive comparator input exceeds th e negative input by more than the specified hysteresis, the output is a logic high. when the negative input ex ceeds the positive by more than the hysteresis, the output is a lo gic low. otherwise, the comparator output retains its present value. refer to table 140, comparator electrical characteristics, on page 223 for details. cinp pi n temperature sensor inpsel innsel cinn pi n comparator internal reference reflvl + - to cout pin to interrupt controller
ps022815-0206 comparator z8 encore! xp ? 4k series product specification 131 the comparator may be powered down to reduce supply current. see the power control register 0 on page 30 for details. because of the propagation delay of the comp arator, it is not reco mmended to enable or reconfigure the comparator without first disabling interrupts and waiting for the com- parator output to settle. doing so can result in spurious in terrupts. the following exam- ple shows how to safely enable the comparator: di ld cmp0, r0 ; load some new configutation nop nop ; wait for output to settle clr irq0 ; clear any spurious interrupts pending ei comparator control register definitions comparator control register the comparator control register (cmp0) co nfigures the comparator inputs and sets the value of the internal voltage reference. inpsel?signal select for positive input 0 = gpio pin used as positive comparator input 1 = temperature sensor used as positive comparator input innsel?signal select for negative input 0 = internal reference disabled, gpio pin used as negative comparator input 1 = internal reference enabled as negative comparator input reflvl?internal reference voltage level (t his reference is independent of the adc voltage reference). note that the 8-pin de vices contain two additional lsbs for increased resolution. for 20-/28-pin devices: table 78. comparator control register (cmp0) bits 7 6 5 4 3 2 1 0 field inpsel innsel reflvl reserved (20-/28-pin) reflvl (8-pin) reset 00010100 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f90h caution:
ps022815-0206 comparator z8 encore! xp ? 4k series product specification 132 0000 = 0.0 v 0001 = 0.2 v 0010 = 0.4 v 0011 = 0.6 v 0100 = 0.8 v 0101 = 1.0 v (default) 0110 = 1.2 v 0111 = 1.4 v 1000 = 1.6 v 1001 = 1.8 v 1010?1111 = reserved for 8-pin devices: 000000 = 0.00v 000001 = 0.05v 000010 = 0.10v 000011 = 0.15v 000100 = 0.20v 000101 = 0.25v 000110 = 0.30v 000111 = 0.35v 001000 = 0.40v 001001 = 0.45v 001010 = 0.50v 001011 = 0.55v 001100 = 0.60v 001101 = 0.65v 001110 = 0.70v 001111 = 0.75v 010000 = 0.80v 010001 = 0.85v 010010 = 0.90v 010011 = 0.95v 010100 = 1.00v (default) 010101 = 1.05v 010110 = 1.10v 010111 = 1.15v 011000 = 1.20v 011001 = 1.25v 011010 = 1.30v 011011 = 1.35v 011100 = 1.40v 011101 = 1.45v 011110 = 1.50v
ps022815-0206 comparator z8 encore! xp ? 4k series product specification 133 011111 = 1.55v 100000 = 1.60v 100001 = 1.65v 100010 = 1.70v 100011 = 1.75v 100100 = 1.80v
ps022815-0206 temperature sensor z8 encore! xp ? 4k series product specification 134 temperature sensor overview the on-chip temperature sensor allows the u ser the ability to measure temperature on the die with either the on-board adc or on-board comparator. this block is factory calibrated for in-circuit software correc tion. uncalibrated accuracy is si gnificantly worse, therefore the temperature sensor is not re commended for uncalibrated use. temperature sensor operation the on-chip temperature sensor is a ptat (pro portional to absolute temperature) topology. a pair of flash option bytes contain the calib ration data. the temperature sensor can be disabled by a bit in the power control register 0 ( page 30 ) to reduce power consumption. the temperature sensor can be directly read by the adc to determine the absolute value of its output. the temperature sensor output is also available as an input to the comparator for threshold type measurement dete rmination. the accuracy of th e sensor when used with the comparator is substantially less than when measured by the adc. if the temperature sensor is routed to the adc, the adc must be configured in unity-gain buffered mode ( see input buffer stage on page 122. ) the value read back from the adc is a signed number, althou gh it is always positive. the sensor is factory-trimmed through the adc using the external 2.0v reference. unless the sensor is re-trimmed for use with a differen t reference, it is most accurate when used with the external 2.0v reference. because this sensor is an on-chip sensor it is recommended that the user account for the difference between ambient and die temperat ure when inferring ambient temperature con- ditions. during normal operation, the die undergoes h eating that will caus e a mismatch between the ambient temperature and that measured by the sensor. for best results, the xp device should be placed into stop mode for suffic ient time such that the die and ambient tem- peratures converge (this time w ill be dependent on the thermal design of the system). the temperature sensor measurement should then be made immediately after recovery from stop mode. the following equation defines the transfer function between the temperature sensor out- put voltage and the die temperature. this is needed for comparat or threshold measure- ments. v = 0.01 * t + 0.65 (where t is the temperatur e in c; v is the sensor output in volts)
ps022815-0206 temperature sensor z8 encore! xp ? 4k series product specification 135 assuming a compensated adc measurement, th e following equation defines the relation- ship between the adc reading and the die temperature: t = (25/128)*(adc - tscal) + 30 (where t is the temperature in c; adc is the 10 bit compensated adc value; and tscal is the temperature sensor calibration value) see temperature sensor calibration data on page 162 for the location of tscal. calibration the temperature sensor undergoes calibration during the manufacturing process and is maximally accurate at 30c. accuracy decreases as measured temperatures move further from the calibration point.
ps022815-0206 flash memory z8 encore! xp ? 4k series product specification 136 flash memory overview the products in the z8 encore! xp ? 4k series features either 4kb (4096), 2kb (2048 bytes), or 1kb (1024) of non-volatile flash memory with read/write/erase capability. the flash memory can be programmed and erased in-circuit by user code or through the on- chip debugger. the flash memory array is a rranged in pages with 512 bytes per page. the 512-byte page is the minimum flash block size that can be era sed. each page is divided into 8 rows of 64 bytes. for program/data protection, the flash memory is also divided into sectors. in the z8 encore! xp ? 4k series, these sectors are 512 bytes in size; each sector maps to a page. page and sector sizes are not equal fo r other members of the z8 encore! ? family. the first 2 bytes of the flash program memory are used as fl ash option bits. refer to the chapter flash option bits on page 148 for more information about their operation. table 79 describes the flash memory configuratio n for each device in the z8 encore! xp ? 4k series. figure 21 illustrates the flash memory arrangement. table 79. z8 encore! xp ? 4k series flash memory configurations part number flash size kb (bytes) flash pages program memory addresses flash sector size (bytes) z8f04xa 4 (4096) 8 0000h?0fffh 512 z8f02xa 2 (2048) 4 0000h?07ffh 512 z8f01xa 1 (1024) 2 0000h?03ffh 512
ps022815-0206 flash memory z8 encore! xp ? 4k series product specification 137 figure 21.flash memory arrangement flash information area the flash information area is separate fro m program memory and is mapped to the address range fe00h to ffffh . this area is readable but can not be erased or overwritten. factory trim values for the anal og peripherals are stored here. factory calibration data for the adc is also stored here. 4kb flash program memory 0000 8 pages/sectors 512 bytes each 01ff 0200 0fff addresses (hex) 03ff 0400 05ff 0600 07ff 0800 09ff 0a00 0bff 0c00 0dff 0e00 2kb flash program memory 0000 4 pages/sectors addresses (hex) 07ff 05ff 0600 03ff 0400 01ff 0200 1kb flash program memory 0000 addresses (hex) 03ff 01ff 0200 2 pages/sectors sector 7 sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0 sector 0 sector 1 sector 0 sector 1 sector 2 sector 3
ps022815-0206 flash memory z8 encore! xp ? 4k series product specification 138 operation the flash controller programs and erases fl ash memory. the flash controller provides the proper flash controls and timing for byte programming, page erase, and mass erase of flash memory. the flash controller contains several protec tion mechanisms to prevent accidental pro- gramming or erasure. these mechanism operat e on the page, sector and full-memory lev- els. the flow chart in figure 22 illustrates basic flash contro ller operation. the following subsections provide details about the variou s operations (lock, unlock, byte program- ming, page protect, page unprotect, page select, page erase, and mass erase) listed in figure 22 .
ps022815-0206 flash memory z8 encore! xp ? 4k series product specification 139 figure 22.flash controller operation flow chart reset page 73h no yes 8ch no yes program/erase enabled 95h no yes write fctl lock state 0 lock state 1 write fctl write fctl byte program page erase write page select register write page select register page in no no unlocked protected sector? writes to page select register in lock state 1 result in a return to lock state 0 page select yes values match? yes
ps022815-0206 flash memory z8 encore! xp ? 4k series product specification 140 flash operation timing using the flash frequency registers before performing either a program or erase operation on flash memory, the user must first configure the flash frequency high an d low byte registers. the flash frequency registers allow programming and erasing of the flash with system clock frequencies rang- ing from 32 khz (32768 hz) through 20 mhz. the flash frequency high and low byte re gisters combine to form a 16-bit value, ffreq , to control timing for flash program and erase operations. the 16-bit binary flash frequency value must contain the system clock frequency (in khz). this value is calcu- lated using the following equation: . flash programming and erasure are not supp orted for system clock frequencies below 32 khz (32768 hz) or above 20 mhz. the flash frequency high and low byte regis- ters must be loaded with the correct valu e to ensure operation of the z8 encore! xp ? 4k series devices. flash code protection ag ainst external access the user code contained within the flash memory can be protected against external access by the on-chip debugger. programming the frp flash option bit prevents reading of the user code with the on-chip de bugger. refer to the chapter flash option bits on page 148 and the chapter on-chip debugger on page 167 for more information. flash code protection against accidental program and erasure the z8 encore! xp ? 4k series provides several levels of protection against accidental program and erasure of the flash memory contents. this protection is provided by a com- bination of the flash option bits, the register locking mechanism, the page select redun- dancy and the sector level protectio n control of the flash controller. flash code protection using the flash option bits the frp and fwp flash option bits combine to prov ide three levels of flash program memory protection as listed in table 80 . refer to the chapter flash option bits on page 148 for more information. ffreq[15:0] system clock frequency (hz) 1000 --------------------- --------------------- ----------------- ----------------- = caution:
ps022815-0206 flash memory z8 encore! xp ? 4k series product specification 141 . flash code protection using the flash controller at reset, the flash controller locks to preven t accidental program or erasure of the flash memory. to program or erase the flash memory, first write the page select register with the target page. unlock the flash controlle r by making two consecutive writes to the flash control register with the values 73h and 8ch , sequentially. the page select register must be rewritten with the target page. if the two page select writes do not match, the con- troller reverts to a locked state. if the two writes match, the selected page becomes active. see figure 22 for details. after unlocking a specific page, the user can enable either page program or erase. writing the value 95h causes a page erase only if the active pa ge resides in a sector that is not pro- tected. any other value written to the flash co ntrol register locks the flash controller. mass erase is not allowed in the user co de but only in thro ugh the debug port. after unlocking a specific page , the user can also write to any byte on that page. after a byte is written, the page remains unlocked, a llowing for subsequent writes to other bytes on the same page. further writes to the fl ash control register cause the active page to revert to a locked state. sector based flash protection the final protection mechanism is implemente d on a per-sector basis. the flash memories of z8 encore! ? devices are divided into at most 8 sectors. a sector is 1/8 of the total size of the flash memory, unl ess this value is smaller than the page size, in which case the sec- tor and page sizes are equa l. on the z8 encore! xp ? 4k series devices, the sector size is 512 bytes, equal to the page size. the sector protect register controls the protecti on state of each flash sector. this register is shared with the page select register. it is accessed by writing 73h followed by 5eh to the flash controller. the next write to the flas h control register targets the sector protect register. the sector protect register is initialized to 0 on reset, putting each sector into an unpro- tected state. when a bit in the sector protec t register is written to 1, the corresponding table 80. flash code protection using the flash option bits fwp flash code protection description 0 programming and erasing disabled for all of flash program memory. in user code programming, page erase, and mass erase are all disabled. mass erase is available through the on-chip debugger. 1 programming, page erase, and mass erase are enabled for all of flash program memory.
ps022815-0206 flash memory z8 encore! xp ? 4k series product specification 142 sector can no longer be written or erased. afte r a bit of the sector protect register has been set, it can not be cleared ex cept by powering down the device. byte programming the flash memory is enabled for byte progr amming after unlocking the flash controller and successfully enabling either mass erase or page erase. when the flash controller is unlocked and mass erase is successfully co mpleted, all program memory locations are available for byte programming. in contrast , when the flash controller is unlocked and page erase is successfully completed, only the locations of the selected page are available for byte programming. an erased flash byte contains all 1?s ( ff h ). the programming operation can only be used to change bits fro m 1 to 0. to change a flash bit (or multiple bits) from 0 to 1 requires execution of eith er the page erase or mass erase commands. byte programming can be accomplished using the on-chip debugger's write memory command or ez8 cpu execution of the ldc or ldci instructions. refer to the ez8 cpu user manual (available for download at www.zilog.com )for a description of the ldc and ldci instructions. while the flash contro ller programs the flash memory, the ez8 cpu idles but the system clock and on-chip peripherals continue to operate. to exit program- ming mode and lock the flash, write any va lue to the flash control register, except the mass erase or page erase commands. the byte at each address of the flash memo ry cannot be programmed (any bits written to 0) more than twice before an erase cycl e occurs. doing so may result in corrupted data at the target byte. page erase the flash memory can be erased one page (512 bytes) at a time. page erasing the flash memory sets all bytes in that page to the value ffh . the flash page select register identi- fies the page to be erased. only a page resi ding in an unprotected sector can be erased. with the flash controller unlocked and the active page set, writing the value 95h to the flash control register initiates the page er ase operation. while th e flash controller exe- cutes the page erase operation, the ez8 cp u idles but the system clock and on-chip peripherals continue to operate. the ez8 cpu resumes operation after the page erase operation completes. if the page erase operation is performed using the on-chip debug- ger, poll the flash status register to determin e when the page erase operation is complete. when the page erase is complete, the flash controller returns to its locked state. mass erase the flash memory can also be mass erased us ing the flash controller, but only by using the on-chip debugger. mass erasing the flas h memory sets all bytes to the value ffh . with the flash controller unlocked and the mass erase successfully enabled, writing the caution:
ps022815-0206 flash memory z8 encore! xp ? 4k series product specification 143 value 63h to the flash control register initiates the mass erase operation. while the flash controller executes the mass erase operation, the ez8 cpu idles but the system clock and on-chip peripherals continue to operate. us ing the on-chip debugger, poll the flash sta- tus register to determine wh en the mass erase operation is complete. when the mass erase is complete, the flash contro ller returns to its locked state. flash controller bypass the flash controller can be bypassed and the control signals for the flash memory brought out to the gpio pins. bypassing the flash controller allows faster row program- ming algorithms by controlling the flash programming signals directly. row programming is recommended for gang pr ogramming applications and large volume customers who do not require in-circuit initia l programming of the flash memory. page erase operations are also supported wh en the flash controller is bypassed. please refer to the document entitled third-party flash programming support for z8 encore! ? for more information abou t bypassing the flash controller. this document is available for download at www.zilog.com . flash controller beh avior in debug mode the following changes in behavior of the fl ash controller occur when the flash control- ler is accessed using the on-chip debugger: ? the flash write protect option bit is ignored. ? the flash sector protect register is ig nored for programming and erase operations. ? programming operations are not limited to the page selected in the page select register. ? bits in the flash sector protect regi ster can be written to one or zero. ? the second write of the page select regist er to unlock the flash controller is not necessary. ? the page select register can be written when the flash controller is unlocked. ? the mass erase command is enabled th rough the flash control register. for security reasons, the flash controller allows only a single page to be opened for write/erase. when writing multiple flash pages, the flash controller must go through the unlock sequence again to select another page. caution:
ps022815-0206 flash memory z8 encore! xp ? 4k series product specification 144 flash control regi ster definitions flash control register the flash controller must be unlocked usin g the flash control (fctl) register before programming or erasing the fl ash memory. writing the sequence 73h 8ch , sequentially, to the flash control register unlocks the fl ash controller. when the flash controller is unlocked, the flash memory ca n be enabled for mass erase or page erase by writing the appropriate enable command to the fctl. pa ge erase applies only to the active page selected in flash page select register. mass erase is enabled only through the on-chip debugger. writing an invalid va lue or an invalid sequence re turns the flash controller to its locked state. the write-only flash contro l register shares its register file address with the read-only flash status register . fcmd?flash command 73h = first unlock command. 8ch = second unlock command. 95h = page erase command (must be third co mmand in sequence to initiate page erase). 63h = mass erase command (mus t be third command in sequence to initiate mass erase). 5eh = enable flash sector protect register access table 81. flash control register (fctl) bits 7 6 5 4 3 2 1 0 field fcmd reset 00000000 r/w wwwwwwww addr ff8h
ps022815-0206 flash memory z8 encore! xp ? 4k series product specification 145 flash status register the flash status (fstat) register indicates the current state of the flash controller. this register can be read at any time. the read-o nly flash status register shares its register file address with the write-o nly flash control register. reserved?must be 0. fstat?flash controller status 000000 = flash controller locked. 000001 = first unlock comm and received (73h written). 000010 = second unlock comm and received (8ch written). 000011 = flash controller unlocked. 000100 = sector protect register selected. 001xxx = program operation in progress. 010xxx = page erase operation in progress. 100xxx = mass erase op eration in progress flash page select register the flash page select (fps) register shares address space with the flash sector protect register. unless the flash controller is unlo cked and written with 5eh, writes to this address target the flash page select register. the register is used to select one of the 8 available flash memory pa ges to be programmed or erased. each flash page contains 512 bytes of flash memory. during a page erase operation, all flash memory having addresses with the most significant 7-bits given by fps[6:0] are chosen fo r program/erase operation. table 82. flash status register (fstat) bits 7 6 5 4 3 2 1 0 field reserved fstat reset 00000000 r/w rrrrrrrr addr ff8h
ps022815-0206 flash memory z8 encore! xp ? 4k series product specification 146 info_en?informat ion area enable 0 = information area us not selected 1 = information area is selected. the inform ation area is mapped into the program mem- ory address space at addresses fe00h through ffffh . page?page select this 7-bit field identifies the flash memory page for page erase and page unlocking. program memory address[15:9] = page[6:0]. for the z8f04xx devices, the upper 4 bits must be zero. for z8f02xx devices, the upper 5 bits must always be 0. for the z8f01xx devices, the upper 6 bits must always be 0. flash sector protect register the flash sector protect (fprot) register is shared with the flash page select register. when the flash control register is written with 73h followed by 5eh, the next write to this address targets the flash sector protect re gister. in all other cases, it targets the flash page select register. this register selects one of the 8 available fl ash memory sectors to be protected. the reset state of each sector protect bit is an unprotected state. after a sector is protected by setting its corresponding register bit, it cannot be un protected (the register bit cannot be cleared) without powering down the device. table 83. flash page select register (fps) bits 7 6 5 4 3 2 1 0 field info_en page reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff9h table 84. flash sector protect register (fprot) bits 7 6 5 4 3 2 1 0 field sprot7 sprot6 sprot5 sprot4 sprot3 sprot2 sprot1 sprot0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff9h
ps022815-0206 flash memory z8 encore! xp ? 4k series product specification 147 sprot7-sprot0?sector protection each bit corresponds to a 512 byte flash secto r. for the z8f04xx devices all bits are used. for the z8f02xx devices, the upper 4 bits are unused. for the z8f01xx devices, the upper 6 bits are unused. flash frequency high and low byte registers the flash frequency high (ffreqh) and lo w byte (ffreql) registers combine to form a 16-bit value, ffreq, to control tim ing for flash program and erase operations. the 16-bit binary flash frequency value must contain the system clock frequency (in khz) and is calculated usin g the following equation:. the flash frequency high and low byte regist ers must be loaded with the correct value to ensure proper operation of the device. also, flash programming and erasure is not supported for system clock frequenci es below 20 khz or above 20 mhz. ffreqh?flash frequency high byte high byte of the 16-bit flash frequency value. ffreql?flash frequency low byte low byte of the 16-bit flash frequency value. table 85. flash frequency high byte register (ffreqh) bits 7 6 5 4 3 2 1 0 field ffreqh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffah table 86. flash frequency low byte register (ffreql) bits 7 6 5 4 3 2 1 0 field ffreql reset 0 r/w r/w addr ffbh ffreq[15:0] ffreqh[7:0],ffreql[7:0] {} system clock frequency 1000 ---------------- ------------------ ------------------ ----------- == caution:
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 148 flash option bits overview programmable flash option bits allow user co nfiguration of certain aspects of z8 encore! xp ? 4k series operation. the feature configur ation data is stored in the flash program memory and loaded into holding registers du ring reset. the features available for control through the flash option bits are: ? watch-dog timer time-out response sele ction?interrupt or system reset ? watch-dog timer always on (enabled at reset) ? the ability to prevent unwanted read acce ss to user code in program memory ? the ability to prevent accidental programming and erasure of all or a portion of the user code in program memory ? voltage brown-out configuration-always enab led or disabled during stop mode to re- duce stop mode power consumption ? oscillator mode selection-for high, medium, a nd low power crystal osci llators, or external rc oscillator ? factory trimming information for the internal precision oscillator and low voltage detec- tion ? factory calibration values for adc, temper ature sensor, and watch-dog timer compensa- tion ? factory serialization and random ized lot identifier (optional) operation option bit configuration by reset each time the flash option bits are programme d or erased, the device must be reset for the change to take effect. during any reset operation (system reset, power on reset, or stop mode recovery), the flash option bits are automatically read from the flash pro- gram memory and written to option configuration register s. the option configuration registers control operation of th e devices within the z8 encore! xp ? 4k series. option bit control is established before the device exits reset and the ez8 cpu begins code execu- tion. the option configuration registers are not part of the register file and are not acces- sible for read or write access.
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 149 option bit types user option bits the user option bits are contained in the first two bytes of program memory. user access to these bits has been provided because these locations contain application-specific device configurations. the information contained here is lost when page 0 of the program mem- ory is erased. trim option bits the trim option bits are contained in the info rmation page of the flash memory. these bits are factory programmed values required to optimize the operation of onboard analog cir- cuitry and cannot be permanently altered by the user. program memory may be erased without endangering these values. it is possible to alter work ing values of these bits by accessing the trim bit address and data regist ers, but these working values are lost after a power loss or any other reset event. there are 32 bytes of trim data. to modify on e of these values the user code must first write a value between 00h and 1fh into the trim bit address register. the next write to the trim bit data register changes the work ing value of the target trim data byte. reading the trim data requires the u ser code to write a value between 00h and 1fh into the trim bit address register. the next read from th e trim bit data register returns the work- ing value of the target trim data byte. the trim address range is from informati on address 20-3f only. the remainder of the information page is not accessible through the trim bit address and data registers. calibration option bits the calibration option bits are also contained in the information page. these bits are fac- tory programmed values intende d for use in software correc ting the device?s analog per- formance. to read these values, the user code must employ the ldc instruction to access the information area of the address space as defined in see flash information area on page 15. serialization bits as an optional feature, zilog is able to provide factory-programmed serialization. for serialized products, the individual devices will be programmed with unique serial num- bers. these serial numbers are binary values, fo ur bytes in length. the numbers increase in size with each device, but gaps in the serial sequence may exist. these serial numbers are stored in the flash information page (see reading the flash infor- mation page on page 150 and serialization data on page 159 for more details) and are unaffected by mass erasure of the device's flash memory. note:
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 150 randomized lot identification bits as an optional feature, zilog is able to pr ovide a factory-programmed random lot identi- fier. with this feature, all devices in a gi ven production lot will be programmed with the same random number. this random number is uniquely regenerated for each successive production lot and is not likely to be repeated. the randomized lot identifier is a 32 byte bi nary value, stored in the flash information page (see reading the flash information page on page 150 and randomized lot identifier on page 159 for more details) and is unaffected by mass erasure of the device's flash mem- ory. reading the flash information page the following code example shows how to r ead data from the flash information area. ; get value at info address 60 (fe60h) ldx fps, #%80 ; enable access to flash info page ld r0, #%fe ld r1, #%60 ldc r2, @rr0 ; r2 now contains the calibration value flash option bit contro l register definitions trim bit address register the trim bit address (trmadr) register contains the target address for an access to the trim option bits. table 87. trim bit address register (trmadr) bits 7 6 5 4 3 2 1 0 field trmadr - trim bit address (00h to 1fh) reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff6h
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 151 trim bit data register the trim bid data (trmdr) register contains th e read or write data for access to the trim option bits. flash option bit address space the first two bytes of flash program memory at addresses 0000h and 0001h are reserved for the user-programmable flash option bits. flash program memory address 0000h wdt_res?watch-dog timer reset 0 = watch-dog timer time-out generates an inte rrupt request. interrupts must be globally enabled for the ez8 cpu to ackno wledge the interrupt request. 1 = watch-dog timer time-out cau ses a system reset. this setting is the default for unpro- grammed (erased) flash. wdt_ao?watch-dog timer always on 0 = watch-dog timer is automatically enable d upon application of system power. watch- dog timer can not be disabled. 1 = watch-dog timer is enabled upon executi on of the wdt instruction. once enabled, the watch-dog timer can only be disabled by a reset or stop mode recovery. this set- ting is the default for un programmed (erased) flash. table 88. trim bit data register (trmdr) bits 7 6 5 4 3 2 1 0 field trmdr - trim bit data reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff7h table 89. flash option bits at program memory address 0000h bits 7 6 5 4 3 2 1 0 field wdt_res wdt_ao osc_sel[1:0] vbo_ao frp reserved fwp reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr program memory 0000h note: u = unchanged by reset. r/w = read/write.
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 152 osc_sel[1:0]?oscillator mode selection 00 = on-chip oscillator configured for use with external rc networks (<4mhz). 01 = minimum power for use with very lo w frequency crystals (32khz to 1.0mhz). 10 = medium power for use with medium fre quency crystals or ceramic resonators (0.5mhz to 5.0mhz). 11 = maximum power for use with high frequ ency crystals (5.0mhz to 20.0mhz). this setting is the default for un programmed (erased) flash. vbo_ao?voltage brown-out protection always on 0 = voltage brown-out protection is disabled in stop mode to reduce total power con- sumption. 1 = voltage brown-out protection is always enabled including during stop mode. this setting is the default for un programmed (erased) flash. frp?flash read protect 0 = user program code is inaccessible. limite d control features are available through the on-chip debugger. 1 = user program code is accessible. all on-chip debugger commands are enabled. this setting is the default for un programmed (erased) flash. reserved?must be 1. fwp?flash write protect this option bit provides flash program memory protection: 0 = programming and erasure disabled for all of flash program memory. programming, page erase, and mass erase through user code is disabled. mass erase is available using the on-chip debugger. 1 = programming, page erase, and mass era se are enabled for all of flash program mem- ory. flash program memory address 0001h reserved?must be 1. xtldis?state of crystal oscillator at reset: table 90. flash options bits at program memory address 0001h bits 7 6 5 4 3 2 1 0 field reserved xtldis reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr program memory 0001h note: u = unchanged by reset. r/w = read/write.
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 153 this bit only enables the crysta l oscillator. its selection as sy stem clock must be done man- ually. 0 = crystal oscillator is enabled during reset, resulting in longer reset timing 1 = crystal oscillator is disabled during reset, resulting in shorter reset timing trim bit address space trim bit address 0000h reserved? altering this re gister may result in incorrect device operation. trim bit address 0001h reserved? altering this re gister may result in incorrect device operation. table 91. trim options bits at address 0000h bits 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0020h note: u = unchanged by reset. r/w = read/write. table 92. trim option bits at 0001h bits 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0021h note: u = unchanged by reset. r/w = read/write. note:
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 154 trim bit address 0002h ipo_trim?internal precision oscillator trim byte contains trimming bits for in ternal precision oscillator. trim bit address 0003h the lvd is available on 8-pin devices only. reserved?must be 1. lvd_trim?low voltage detect trim this trimming affects the low voltage dete ction threshold. each lsb represents a 50mv change in the threshold level. alte rnatively, the low voltage threshold may be computed from the options bi t value by the following equation: lvd_lvl = 3.2v - lvd_trim * 0.05v table 93. trim option bits at 0002h (tipo) bits 7 6 5 4 3 2 1 0 field ipo_trim reset u r/w r/w addr information page memory 0022h note: u = unchanged by reset. r/w = read/write. table 94. trim option bits at address 0003h (tlvd) bits 7 6 5 4 3 2 1 0 field reserved lvd_trim reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0023h note: u = unchanged by reset. r/w = read/write. lvd threshold (v) lv d_tr im minimum typic al maximum description 00000 tbd 3.20 tbd maximum lvd threshold 00001 tbd 3.15 tbd note:
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 155 trim bit address 0004h reserved? altering this re gister may result in incorrect device operation. zilog calibration data adc calibration data 00010 tbd 3.10 tbd 00011 tbd 3.05 tbd 00100 to 01010 tbd 3.00 to 2.79 tbd default on reset and to be programmed into flash before customer delivery to ensure 2.7v operation. 01010 to 11111 tbd 2.70 to 1.65 tbd minimum lvd threshold table 95. trim option bits at 0004h bits 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0024h note: u = unchanged by reset. r/w = read/write. table 96. adc calibration bits bits 7 6 5 4 3 2 1 0 field adc_cal reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0060h?007dh note: u = unchanged by reset. r/w = read/write. lvd threshold (v) lv d_tr im minimum typic al maximum description
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 156 adc_cal?analog to digital converter calibration values contains factory calibrated values for adc gain and offset compensation. each of the ten supported modes has one byte of offset calibration and two bytes of gain calibration. these values are read by user software to compensate adc measurements as detailed in software compensation procedure using factory calibration data on page 119 . the loca- tion of each calibration byte is provided in table 97 . table 97. adc calibration data location info page address memory address compensation usage adc mode reference type 60 fe60 offset single-ended unbuffered internal 2.0v 08 fe08 gain high byte single-ended unbuffered internal 2.0v 09 fe09 gain low byte single-ended unbuffered internal 2.0v 63 fe63 offset single-ended unbuffered internal 1.0v 0a fe0a gain high byte single-ended unbuffered internal 1.0v 0b fe0b gain low byte single-ended unbuffered internal 1.0v 66 fe66 offset single-ended unbuffered external 2.0v 0c fe0c gain high byte single-ended unbuffered external 2.0v 0d fe0d gain low byte single-ended unbuffered external 2.0v 69 fe69 offset single ended 1x buffered internal 2.0v 0e fe0e gain high byte single en ded 1x buffered internal 2.0v 0f fe0f gain low byte single ende d 1x buffered internal 2.0v 6c fe6c offset single ended 1x buffered external 2.0v 10 fe10 gain high byte single ended 1x buffered external 2.0v 11 fe11 gain low byte single ended 1x buffered external 2.0v 6f fe6f offset differential unbuffered internal 2.0v 12 fe12 positive gain high byte differential unbuffered internal 2.0v 13 fe13 positive gain low byte differential unbuffered internal 2.0v 30 fe30 negative gain high byte differential unbuffered internal 2.0v 31 fe31 negative gain low byte differential unbuffered internal 2.0v 72 fe72 offset differential unbuffered internal 1.0v
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 157 14 fe14 positive gain high byte differential unbuffered internal 1.0v 15 fe15 positive gain low byte differential unbuffered internal 1.0v 32 fe32 negative gain high byte differential unbuffered internal 1.0v 33 fe33 negative gain low byte differential unbuffered internal 1.0v 75 fe75 offset differential unbuffered external 2.0v 16 fe16 positive gain high byte differential unbuffe red external 2.0v 17 fe17 positive gain low byte differential unbuffe red external 2.0v 34 fe34 negative gain high byte differential unbuffe red external 2.0v 35 fe35 negative gain low byte differential unbuffe red external 2.0v 78 fe78 offset differential 1x buffered internal 2.0v 18 fe18 positive gain high byte differential 1x buffered internal 2.0v 19 fe19 positive gain low byte differential 1x buffered internal 2.0v 36 fe36 negative gain high byte differential 1x buffered internal 2.0v 37 fe37 negative gain low byte differential 1x buffered internal 2.0v 7b fe7b offset differential 1x buffered external 2.0v 1a fe1a positive gain high byte differential 1x buffered external 2.0v 1b fe1b positive gain low byte differential 1x buffered external 2.0v table 97. adc calibration data location (continued) info page address memory address compensation usage adc mode reference type
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 158 watchdog timer calibration data wdtcalh?watchdog timer calibration high byte the wdtcalh and wdtcall bytes, when load ed into the watchdog timer reload reg- isters result in a one second timeout at room temperature and 3.3v supply voltage. to use the watch-dog timer calibration, user code must load wd tu with 0x00, wdth with wdtcalh and wdtl with wdtcall. wdtcall?watchdog timer calibration low byte the wdtcalh and wdtcall bytes, when load ed into the watchdog timer reload reg- isters result in a one second timeout at room temperature and 3.3v supply voltage. to use the watchdog timer ca libration, user code must load wdtu with 0x00, wdth with wdtcalh and wdtl with wdtcall. 38 fe38 negative gain high byte differential 1x buffered external 2.0v 39 fe39 negative gain low byte differential 1x buffered external 2.0v table 98. watchdog calibration high byte at 007eh (wdtcalh) bits 7 6 5 4 3 2 1 0 field wdtcalh reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 007eh note: u = unchanged by reset. r/w = read/write. table 99. watchdog calibration low byte at 007fh (wdtcall) bits 7 6 5 4 3 2 1 0 field wdtcall reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 007fh note: u = unchanged by reset. r/w = read/write. table 97. adc calibration data location (continued) info page address memory address compensation usage adc mode reference type
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 159 serialization data s_num? serial number byte the serial number is a unique four-byte binary value. randomized lot identifier rand_lot? randomized lot id the randomized lot id is a 32-byte binary value that changes fo r each production lot. table 100. serial number at 001c - 001f (s_num) bits 7 6 5 4 3 2 1 0 field s_num reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 001c-001f note: u = unchanged by reset. r/w = read/write. table 101. serialization data locations info page address memory address usage 1c fe1c serial number byte 3 (most significant) 1d fe1d serial number byte 2 1e fe1e serial number byte 1 1f fe1f serial number byte 0 (least significant) table 102. lot identifi cation number (rand_lot) bits 7 6 5 4 3 2 1 0 field rand_lot reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr interspersed throughout information page memory note: u = unchanged by reset. r/w = read/write.
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 160 table 103. randomized lot id locations info page address memory address usage 3c fe3c randomized lot id byte 31 (most significant) 3d fe3d randomized lot id byte 30 3e fe3e randomized lot id byte 29 3f fe3f randomized lot id byte 28 58 fe58 randomized lot id byte 27 59 fe59 randomized lot id byte 26 5a fe5a randomized lot id byte 25 5b fe5b randomized lot id byte 24 5c fe5c randomized lot id byte 23 5d fe5d randomized lot id byte 22 5e fe5e randomized lot id byte 21 5f fe5f randomized lot id byte 20 61 fe61 randomized lot id byte 19 62 fe62 randomized lot id byte 18 64 fe64 randomized lot id byte 17 65 fe65 randomized lot id byte 16 67 fe67 randomized lot id byte 15 68 fe68 randomized lot id byte 14 6a fe6a randomized lot id byte 13 6b fe6b randomized lot id byte 12 6d fe6d randomized lot id byte 11 6e fe6e randomized lot id byte 10 70 fe70 randomized lot id byte 9 71 fe71 randomized lot id byte 8 73 fe73 randomized lot id byte 7 74 fe74 randomized lot id byte 6 76 fe76 randomized lot id byte 5 77 fe77 randomized lot id byte 4
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 161 79 fe79 randomized lot id byte 3 7a fe7a randomized lot id byte 2 7c fe7c randomized lot id byte 1 7d fe7d randomized lot id byte 0 (least significant) table 103. randomized lot id locations (continued) info page address memory address usage
ps022815-0206 flash option bits z8 encore! xp ? 4k series product specification 162 temperature sensor calibration data tscalh ? temperature sensor calibration high byte the tscalh and tscall bytes co mbine to form the temperature sensor offset calibra- tion value. for usage details, see temperature sensor operation on page 134 . tscall ? temperature sens or calibration low byte the tscalh and tscall bytes co mbine to form the temperature sensor offset calibra- tion value. for usage details, see temperature sensor operation on page 134 . table 104. temperature sensor calibration high byte at 003a (tscalh) bits 7 6 5 4 3 2 1 0 field tscalh reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 003a note: u = unchanged by reset. r/w = read/write. table 105. temperature sensor calibration low byte at 003b (tscall) bits 7 6 5 4 3 2 1 0 field tscall reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 003b note: u = unchanged by reset. r/w = read/write.
ps022815-0206 non-volatile data storage z8 encore! xp ? 4k series product specification 163 non-volatile data storage overview the z8 encore! xp ? 4k series devices contain a non- volatile data storage (nvds) ele- ment of up to 128 bytes. this memory can perform over 100,000 write cycles. operation the nvds is implemented by special purpose zi log software stored in areas of program memory not accessible to the user. these spec ial-purpose routines u se the flash memory to store the data. the routines incorporate a dynamic addressing scheme to maximize the write/erase endurance of the flash. different members of the z8 encore! xp ? 4k series feature multiple nvds array sizes. see z8 encore! xp ? 4k series family part selection guide on page 2 for details. nvds code interface two routines are required to access the nvds: a write routine and a read routine. both of these routines are accessed with a call instruc tion to a pre-defined address outside of the user-accessible program memory. both the nvds address and data are single-byte values. because these routines disturb the working regi ster set, user code must ensure that any required working register values are preser ved by pushing them onto the stack or by changing the working register pointer just prior to nvds execution. during both read and write accesses to the n vds, interrupt service is not disabled. any interrupts that occur during the nvds executio n must take care not to disturb the working register and existing stack contents or el se the array may become corrupted. disabling interrupts before executing nvds operations is recommended. use of the nvds requires 15 bytes of availa ble stack space. also, the contents of the working register set are overwritten. for correct nvds operation, the flash freque ncy registers must be programmed based on the system clock frequency ( see flash operation timing using the flash frequency registers on page 140 ). note:
ps022815-0206 non-volatile data storage z8 encore! xp ? 4k series product specification 164 byte write to write a byte to the nvds array, the user code must first push the ad dress, then the data byte onto the stack. th e user code issues a call instruction to the address of the byte- write routine (0x10b3). at the re turn from the sub-routine, the write status byte resides in working register r0. the bit fields of this status byte are defined in table 106 . the con- tents of the status byte are undefined for wr ite operations to illega l addresses. also, user code should pop the address and data bytes off the stack. the write routine uses 13 bytes of stack space in addition to the two bytes of address and data pushed by the user. su fficient memory must be available for this stack usage. because of the flash memory architecture, nvds writes exhibit a non-uniform execution time. in general, a write takes 251 s (assuming a 20mhz system clock). every 400 to 500 writes, however, a maintenance operation is n ecessary. in this rare occurrence, the write takes up to 61ms to complete . slower system clock speeds result in proportionally higher execution times. nvds byte writes to invalid addresses (those exceeding the nvds array size) have no effect. illegal write operations have a 2 s execution time. reserved?must be 0. rcpy?recopy subroutine executed a recopy subroutine was executed. these oper ations take significantly longer than a normal write operation. pf?power failure indicator a power failure or system reset occurred duri ng the most recent attempted write to the nvds array. aw?address write error an address byte failure occurred during the most recent attempted write to the nvds array. dwe?data write error a data byte failure occurred during the mo st recent attempted write to the nvds array. table 106. write status byte bits 7 6 5 4 3 2 1 0 field reserved rcpy pf awe dwe default va l u e 00000000
ps022815-0206 non-volatile data storage z8 encore! xp ? 4k series product specification 165 byte read to read a byte from the nvds array, user co de must first push the address onto the stack. user code issues a call instruction to the address of th e byte-read routine (0x1000). at the return from the sub-routine, the read byte resides in work ing register r0, and the read status byte resides in working register r1. the contents of the status byte are undefined for read operations to illegal addresses. also, the us er code should pop the address byte off the stack. the read routine uses 9 bytes of stack space in addition to the one byte of address pushed by the user. sufficient memory must be available for this stack usage. because of the flash memory architecture, nvds reads exhibit a non-uniform execution time. a read operation takes between 44 s and 489 s (assuming a 20 mhz system clock). slower system clock speeds result in proportionally higher execution times. nvds byte reads from invalid addresses (those exceeding the nvds array size) return 0xff. illegal read operations have a 2 s execution time. the status byte returned by the nvds read routine is zero for successful read, as deter- mined by a crc check. if the status byte is non-zero, there was a corrupted value in the nvds array at the location being read. in this case, the value returned in r0 is the byte most recently written to the arra y that does not have a crc error. power failure protection the nvds routines employ e rror checking mechanisms to ensure a power failure endan- gers only the most recently written byte. byte s previously written to the array are not per- turbed. a system reset (such as a pin reset or watch dog timer reset) that occurs during a write operation also perturbs the byt e currently being written. all other bytes in the array are unperturbed. optimizing nvds memory usage for execution speed as table 107 shows, the nvds read time varies drastically, this discrepancy being a trade-off for minimizing the frequency of write s that require post-write page erases. the nvds read time of address n is a function of the number of writes to addresses other than n since the most recent write to address n, as well as the number of writes since the most recent page erase. neglecting effects caused by page erases and results caused by the ini- tial condition in which the nvds is blank, a rule of thumb is that every write since the most recent page erase causes read times of unwritten addresses to increase by 1 s, up to a maximum of (511-nvds_size) s.
ps022815-0206 non-volatile data storage z8 encore! xp ? 4k series product specification 166 if nvds read performance is critical to your so ftware architecture, there are some things you can do to optimize your code for speed, listed in order fro m most helpful to least help- ful: ? periodically refresh all addresses that are used . the optimal use of nvds in terms of speed is to rotate the writes evenly among all addresses planned to use, bringing all reads closer to the minimum read time. because the minimu m read time is much less than the write time, however, actual speed benefits are not always realized. ? use as few unique addresses as possible: this helps to optimize the impact of refreshing as well as minimize the requirement for it. table 107. nvds read time operation minimum latency maximum latency read (16 byte array) 875 9961 read (64 byte array) 876 8952 read (128 byte array) 883 7609 write (16 byte array) 4973 5009 write (64 byte array) 4971 5013 write (128 byte array) 4984 5023 illegal read 43 43 illegal write 31 31
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 167 on-chip debugger overview the z8 encore! xp ? devices contain an integrated on-chip debugger (ocd) that pro- vides advanced debugging features including: ? reading and writing of the register file ? reading and writing of program and data memory ? setting of breakpoints and watchpoints ? executing ez8 cpu instructions ? debug pin sharing with general-purpose input- output function to maximize pins available to the user (8-pin product only) architecture the on-chip debugger consists of four primar y functional blocks: tr ansmitter, receiver, auto-baud detector/generator, and debug controller. figure 23 illustrates the architecture of the on-chip debugger figure 23.on-chip debugger block diagram auto-baud system clock transmitter receiver dbg pin debug controller ez8 cpu control detector/generator
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 168 operation ocd interface the on-chip debugger uses the dbg pin for co mmunication with an external host. this one-pin interface is a bi-directional, open-drain interface that transmits and receives data. data transmission is half-duplex, in that tr ansmit and receive cannot occur simultaneously. the serial data on the dbg pin is sent us ing the standard asynchronous data format defined in rs-232. this pin creates an interface from the z8 encore! xp ? 4k series prod- ucts to the serial port of a host pc using minimal external hardware.two different methods for connecting the dbg pin to an rs -232 interface are depicted in figures 24 and 25 . the recommended method is the buffer ed implementation depicted in figure 25 . the dbg pin must always be connected to v dd through an external pull-up resistor. for operation of the on-chip debugger, all power pins (v dd and av dd ) must be supplied with power, and all ground pins (v ss and av ss ) must be properly grounded. the dbg pin is open-drain and must always be connected to v dd through an external pull-up resistor to insure proper operation. figure 24.interfacing the on-chip debugger?s dbg pin with an rs-232 interface (1) caution: rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10kohm schottky diode
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 169 figure 25.interfacing the on-chip debugger?s dbg pin with an rs-232 interface (2) debug mode the operating characteristics of the devices in debug mode are: ? the ez8 cpu fetch unit stops, idling the ez8 cp u, unless directed by the ocd to execute specific instructions ? the system clock operates unless in stop mode ? all enabled on-chip peripheral s operate unless in stop mode ? automatically exits halt mode ? constantly refreshes the watch-dog timer, if enabled entering debug mode ? the device enters debug mode after the ez 8 cpu executes a brk (breakpoint) instruc- tion. ? if the dbg pin is held low during the most re cent clock cycle of system reset, the part enters debug mode upon exiting system reset. (20-/28-pin products only.) ? if the pa2/reset pin is held low while a 32-bit ke y sequence is issued to the pa0/dbg pin, the dbg feature is unlocked. after releasing pa2/reset , it will be pulled high. at this point, the pa0/dbg pin may be used to autobaud and cause the device to enter de- bug mude. see ocd unlock sequence (8-p in devices only) on page 171. exiting debug mode the device exits debug mode following any of these operations: ? clearing the dbgmode bit in the ocd control register to 0. rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10kohm open-drain buffer
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 170 ? power-on reset ? voltage brown-out reset ? watch-dog timer reset ? asserting the reset pin low to initiate a reset. ? driving the dbg pin low while the device is in stop mode initiates a system reset. ocd data format the ocd interface uses the asynchronous data format defined for rs-232. each character is transmitted as 1 start bit, 8 data bits (lea st-significant bit first), and 1.5 stop bits as shown in figure 26 . figure 26.ocd data format ocd auto-baud detector/generator to run over a range of baud rates (data bits per second) with various system clock frequen- cies, the on-chip debugger contains an auto -baud detector/generator. after a reset, the ocd is idle until it receives data. the ocd re quires that the first character sent from the host is the character 80h . the character 80h has eight continuous bits low (one start bit plus 7 data bits), framed between high bits. the auto-baud detector measures this period and sets the ocd baud rate generator accordingly. the auto-baud detector/generator is clocke d by the system clock. the minimum baud rate is the system clock frequency divided by 512. for optimal operation with asynchro- nous datastreams, the maximum recommended baud rate is the system clock frequency divided by 8. the maximum possible baud ra te for asynchronous datastreams is the sys- tem clock frequency divided by 4, but this th eoretical maximum is possible only for low noise designs with clean signals. table 108 lists minimum and recommended maximum baud rates for sample crystal frequencies. table 108. ocd baud-rate limits system clock frequency (mhz) recommended maximum baud rate (kbps) recommended standard pc baud rate (bps) minimum baud rate (kbps) 20.0 2500.0 1,843,200 39 startd0d1d2d3d4d5d6d7stop
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 171 if the ocd receives a serial break (nine or more continuous bits low) the auto-baud detector/generator resets. reconfigure the auto-baud detector/generator by sending 80h . ocd serial errors the on-chip debugger can detect any of th e following error conditions on the dbg pin: ? serial break (a minimum of nine continuous bits low) ? framing error (received stop bit is low) ? transmit collision (ocd and host simultan eous transmission de tected by the ocd) when the ocd detects one of these errors, it aborts any command currently in progress, transmits a four character long serial brea k back to the host, and resets the auto-baud detector/generator. a framing error or tran smit collision may be caused by the host sending a serial break to the ocd. because of the open-drain natu re of the interface, returning a serial break break back to the host only extends the length of the serial break if the host releases the serial break early. the host transmits a serial break on the dbg pin when first connec ting to the z8 encore! xp ? 4k series devices or when recovering fro m an error. a serial break from the host resets the auto-baud generator/detector bu t does not reset the ocd control register. a serial break leaves the device in debug mode if that is the current mode. the ocd is held in reset until the end of the serial brea k when the dbg pin returns high. because of the open-drain nature of the dbg pin, the host can send a serial break to the ocd even if the ocd is transmitting a character. ocd unlock sequence (8-pin devices only) because of pin-sharing on the 8-pin device, an unlock sequence must be performed to access the dbg pin. if this squence is not comp leted during a system reset, then the pa0/ dbg pin functions only as a gpio pin. the following sequence unlocks the dbg pin: 1. hold pa2/reset low. 1.0 125.0 115,200 1.95 0.032768 (32khz) 4.096 2400 0.064 table 108. ocd baud-rate limits system clock frequency (mhz) recommended maximum baud rate (kbps) recommended standard pc baud rate (bps) minimum baud rate (kbps)
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 172 2. wait 5ms for the internal reset sequence to complete. 3. send the following bytes serially to the debug pin: dbg 80h (autobaud) dbg ebh dbg 5ah dbg 70h dbg cdh (32-bit unlock key) 4. release pa2/reset . the pa0/dbg pin is now identical in function to that of the dbg pin on the 20-/28-pin device. to en ter debug mode, re-autobaud and write 80h to the ocd control register. ( see on-chip debugger commands on page 172. ) breakpoints execution breakpoints are generated using the brk instruction (opcode 00h ). when the ez8 cpu decodes a brk instruction, it signal s the on-chip debugger. if breakpoints are enabled, the ocd enters debug mode and id les the ez8 cpu. if breakpoints are not enabled, the ocd ignores the brk signal and the brk instruction operates as an nop instruction. breakpoints in flash memory the brk instruction is opcode 00h , which corresponds to the fu lly programmed state of a byte in flash memory. to implement a breakpoint, write 00h to the required break address, overwriting the current instruction. to remove a breakpoi nt, the corresponding page of flash memory must be erased an d reprogrammed with the original data. runtime counter the on-chip debugger contains a 16-bit run time counter. it counts system clock cycles between breakpoints. the counter starts co unting when the on-chip debugger leaves debug mode and stops counting when it ente rs debug mode again or when it reaches the maximum count of ffffh . on-chip debugger commands the host communicates to the on-chip debugger by sending ocd commands using the dbg interface. during normal operation, on ly a subset of the ocd commands are avail- able. in debug mode, all ocd commands beco me available unless the user code and control registers are protected by program ming the flash read protect option bit ( frp ). the flash read protect option bit prevents the code in memory from being read out of the z8 encore! xp ? 4k series products. when this option is enabled, several of the ocd
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 173 commands are disabled. table 109 on page 177 is a summary of the on-chip debugger commands. each ocd command is described in further detail in the bulleted list follow- ing this table. table 109 also indicates those commands that operate when the device is not in debug mode (normal operation) and those commands that are disabled by program- ming the flash read protect option bit. in the following bulleted list of ocd comman ds, data and commands sent from the host to the on-chip debugger are identified by ? dbg command/data ?. data sent from the on-chip debugger back to the host is identified by ? dbg data ? debug command command byte enabled when not in debug mode? disabled by flash read protect option bit read ocd revision 00h yes ? reserved 01h ? ? read ocd status register 02h yes ? read runtime counter 03h ? ? write ocd control register 04h yes cannot clear dbgmode bit read ocd control register 05h yes ? write program counter 06h ? disabled read program counter 07h ? disabled write register 08h ? only writes of the flash memory control registers are allowed. additionally, only the mass erase command is allowed to be written to the flash control register. read register 09h ? disabled write program memory 0ah ? disabled read program memory 0bh ? disabled write data memory 0ch ? yes read data memory 0dh ? ? read program memory crc 0eh ? ? reserved 0fh ? ? step instruction 10h ? disabled stuff instruction 11h ? disabled execute instruction 12h ? disabled reserved 13h?ffh ? ?
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 174 ? read ocd revision (00h) ?the read ocd revision command determines the ver- sion of the on-chip debugger. if ocd comman ds are added, removed, or changed, this revision number changes. dbg 00h dbg ocdrev[15:8] (major revision number) dbg ocdrev[7:0] (minor revision number) ? read ocd status register (02h) ?the read ocd status register command reads the ocdstat register. dbg 02h dbg ocdstat[7:0] ? read runtime counter (03h) ?the runtime counter counts system clock cycles in between breakpoints. the 16-bit runtime counter counts up from 0000h and stops at the maximum count of ffffh . the runtime counter is overwritten during the write memo- ry, read memory, write register, read regi ster, read memory crc, step instruction, stuff instruction, and execute instruction commands. dbg 03h dbg runtimecounter[15:8] dbg runtimecounter[7:0] ? write ocd control register (04h) ?the write ocd control register command writes the data that follows to the ocdctl re gister. when the flash read protect option bit is enabled, the dbgmode bit ( ocdctl [7]) can only be set to 1, it cannot be cleared to 0 and the only method of returning the device to normal operating m ode is to reset the device. dbg 04h dbg ocdctl[7:0] ? read ocd control register (05h) ?the read ocd control register command reads the value of the ocdctl register. dbg 05h dbg ocdctl[7:0] ? write program counter (06h) ?the write program counter command writes the data that follows to the ez8 cpu?s program counte r (pc). if the device is not in debug mode or if the flash read protect option bit is en abled, the program counter (pc) values are discarded. dbg 06h dbg programcounter[15:8] dbg programcounter[7:0]
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 175 ? read program counter (07h) ?the read program counte r command reads the value in the ez8 cpu?s program counter (pc). if the device is not in debug mode or if the flash read protect option bit is enabled, this command returns ffffh . dbg 07h dbg programcounter[15:8] dbg programcounter[7:0] ? write register (08h) ?the write register command writes data to the register file. data can be written 1?256 bytes at a time (256 bytes can be written by setting size to 0). if the device is not in debug mode, the address and data values are discarded. if the flash read protect option bit is enabled, only writes to the flash control registers are allowed and all other register write data values are discarded. dbg 08h dbg {4?h0,register address[11:8]} dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes ? read register (09h) ?the read register command read s data from the register file. data can be read 1?256 bytes at a time (256 bytes can be read by setting size to 0). if the device is not in debug mode or if the flash read protect option bit is enabled, this com- mand returns ffh for all the data values. dbg 09h dbg {4?h0,register address[11:8] dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes ? write program memory (0ah) ?the write program memory command writes data to program memory. this command is equivale nt to the ldc and ldci instructions. data can be written 1?65536 bytes at a time (65536 bytes can be written by setting size to 0). the on-chip flash controller must be writte n to and unlocked for the programming oper- ation to occur. if the flash controller is not unlocked, the data is discarded. if the device is not in debug mode or if the flash read pr otect option bit is enab led, the data is dis- carded. dbg 0ah dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read program memory (0bh) ?the read program memory command reads data from program memory. this command is equiva lent to the ldc and ldci instructions.
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 176 data can be read 1?65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode or if the flash read protect option bit is enabled, this command returns ffh for the data. dbg 0bh dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? write data memory (0ch) ?the write data memory co mmand writes data to data memory. this command is equivalent to the ld e and ldei instructions. data can be writ- ten 1?65536 bytes at a time (6553 6 bytes can be written by setting size to 0). if the device is not in debug mode or if the flash read pr otect option bit is enab led, the data is dis- carded. dbg 0ch dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read data memory (0dh) ?the read data memory co mmand reads from data mem- ory. this command is equivalent to the lde and ldei instructions. data can be read 1 to 65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode, this command returns ffh for the data. dbg 0dh dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read program memory crc (0eh) ?the read program memory crc command computes and returns the cyclic redundancy check (crc) of program memory using the 16-bit crc-ccitt polynomial. if the device is not in debug mode, this command re- turns ffffh for the crc value. unlike most othe r ocd read commands, there is a delay from issuing of the command until the ocd returns the data. the ocd reads the program memory, calculates the crc value, and return s the result. the delay is a function of the program memory size and is approximately equal to the sy stem clock period multiplied by the number of bytes in the program memory. dbg 0eh dbg crc[15:8] dbg crc[7:0]
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 177 ? step instruction (10h) ?the step instruction command steps one assembly instruction at the current program counter (pc) location. if the device is not in debug mode or the flash read protect option bit is enab led, the ocd ignores this command. dbg 10h ? stuff instruction (11h) ?the stuff instruction command steps one assembly instruction and allows specification of the first byte of the instruction. the remaining 0-4 bytes of the instruction are read from program memory. th is command is useful for stepping over in- structions where the first byte of the instru ction has been overwritten by a breakpoint. if the device is not in debug mode or the flas h read protect option bit is enabled, the ocd ignores this command. dbg 11h dbg opcode[7:0] ? execute instruction (12h) ?the execute instruction command allows sending an en- tire instruction to be executed to the ez8 cpu. this command can also step over break- points. the number of bytes to send for the instruction depends on the opcode. if the device is not in debug mode or the flash read pr otect option bit is enabled, this command reads and discards one byte. dbg 12h dbg 1-5 byte opcode on-chip debugger control register definitions ocd control register the ocd control register controls the state of the on-chip debugger. this register is used to enter or exit debu g mode and to enable the brk instruction. it can also reset the z8 encore! xp ? 4k series device. a reset and stop function can be achieved by writing 81h to this register. a reset and go function can be achieved by writing 41h to this register. if the device is in debug mode, a run function can be implemented by writing 40h to this register. . dbgmode?debug mode the device enters debug mode when this b it is 1. when in debug mode, the ez8 cpu table 109. ocd control register (ocdctl) bits 7 6 5 4 3 2 1 0 field dbgmode brken dbgack reserved rst reset 00000000 r/w r/wr/wr/wrrrrr/w
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 178 stops fetching new instructions. clearing this bit causes the ez8 cpu to restart. this bit is automatically set when a brk instruction is decoded and breakpoints are enabled. if the flash read protect option bit is enabled, th is bit can only be cleared by resetting the device. it cannot be written to 0. 0 = the z8 encore! xp ? 4k series device is operating in normal mode. 1 = the z8 encore! xp ? 4k series device is in debug mode. brken?breakpoint enable this bit controls the behavior of the brk instruction (opcode 00h ). by default, break- points are disabled and the brk instruction behaves similar to an nop instruction. if this bit is 1, when a brk instruction is decoded, the dbgmode bit of the ocdctl register is automatically set to 1. 0 = breakpoints are disabled. 1 = breakpoints are enabled. dbgack?debug acknowledge this bit enables the debug acknowledge feature. if this bit is set to 1, the ocd sends a debug acknowledge character ( ffh ) to the host when a breakpoint occurs. 0 = debug acknowledge is disabled. 1 = debug acknowledge is enabled. reserved?must be 0. rst?reset setting this bit to 1 resets th e z8f04xa family de vice. the device go es through a normal power-on reset sequence with the exception th at the on-chip debugger is not reset. this bit is automatically cleared to 0 at the end of reset. 0 = no effect. 1 = reset the flash read protect option bit device. ocd status register the ocd status register reports status inform ation about the current state of the debugger and the system. dbg?debug status 0 = normal mode 1 = debug mode table 110. ocd status register (ocdstat) bits 7 6 5 4 3 2 1 0 field dbg halt frpenb reserved reset 00000000 r/w rrrrrrrr
ps022815-0206 on-chip debugger z8 encore! xp ? 4k series product specification 179 halt?halt mode 0 = not in halt mode 1 = in halt mode frpenb?flash read protect option bit enable 0 = frp bit enabled, that allows disabling of many ocd commands 1 = frp bit has no effect reserved?must be 0.
ps022815-0206 oscillator control z8 encore! xp ? 4k series product specification 180 oscillator control overview the z8 encore! xp ? 4k series devices uses five possi ble clocking schemes, each user- selectable: ? internal precision trimmed rc oscillator (ipo) ? on-chip oscillator using off-c hip crystal or resonator ? on-chip oscillator using external rc network ? external clock drive ? on-chip low precision watch-dog timer oscillator in addition, z8 encore! xp ? 4k series devices contain clock failure detection and recov- ery circuitry, allowing continued operation desp ite a failure of the system clock oscillator. operation this chapter discusses the logic used to select the system clock and handle primary oscil- lator failures. a description of the specific op eration of each oscill ator is outlined else- where in this document. the detailed descrip tion of the watch-dog timer oscillator starts on page 83 , the internal precision osc illator description begins on page 190 , and the chap- ter outlining the crystal oscillator begins on page 185 of this document. system clock selection the oscillator control block sel ects from the available clocks. table 111 details each clock source and its usage.
ps022815-0206 oscillator control z8 encore! xp ? 4k series product specification 181 unintentional accesses to the oscillator cont rol register can actually stop the chip by switching to a non-functioning oscillator. to prevent this condition, the oscillator con- trol block employs a register unlocking/locking scheme. osc control register unlocking/locking to write the oscillator control register, unlo ck it by making two writes to the oscctl register with the values e7h followed by 18h . a third write to the oscctl register changes the value of the actual register and retu rns the register to a locked state. any other sequence of oscillator control register writes has no effect. the values written to unlock the register must be ordered correctly, but are not necessarily consecutive. it is possible to write to or read from other registers within the unlockin g/locking operation. table 111. oscillator conf iguration and selection clock source characteristics required setup internal precision rc oscillator ? 32.8 khz or 5.53 mhz ? high accuracy when trimmed ? no external components required ? unlock and write oscillator control register (oscctl) to enable and select oscillator at either 5.53 mhz or 32.8 khz external crystal/ resonator ? 32 khz to 20 mhz ? very high accuracy (dependent on crystal or resonator used) ? requires external components ? configure flash option bits for correct external oscillator mode ? unlock and write oscctl to enable crystal oscillator, wait for it to stabilize and select as system clock (if the xtldis option bit has been de- asserted, no waiting is required) external rc oscillator ? 32 khz to 4 mhz ? accuracy dependent on external components ? configure flash option bits for correct external oscillator mode ? unlock and write oscctl to enable crystal oscillator and select as system clock external clock drive ? 0 to 20 mhz ? accuracy dependent on external clock source ? write gpio registers to configure pb3 pin for external clock function ? unlock and write oscctl to select external system clock ? apply external clock signal to gpio internal watchdog timer oscillator ? 10 khz nominal ? low accuracy; no external components required ? low power consumption ? enable wdt if not enabled and wait until wdt oscillator is operating. ? unlock and write oscillator control register (oscctl) to enable and select oscillator caution:
ps022815-0206 oscillator control z8 encore! xp ? 4k series product specification 182 when selecting a new clock sour ce, the system clock oscillato r failure detection circuitry and the watch-dog timer oscillator failure circuitry must be disabled. if sofen and wofen are not disabled prior to a clock switc h-over, it is possible to generate an inter- rupt for a failure of either oscillator. the failure detection circu itry can be enabled any- time after a successful write of oscsel in the oscctl register. the internal precision oscillator is enabled by default. if the user code changes to a differ- ent oscillator, it may be appr opriate to disable the ipo fo r power savings. disabling the ipo does not occur automatically. clock failure detection and recovery system clock oscillator failure the z8f04xa family devices can generate no n-maskable interrupt-like events when the primary oscillator fails. to maintain system fu nction in this situatio n, the clock failure recovery circuitry automatically forces the watc h-dog timer oscillator to drive the system clock. the watch-dog timer oscillator must be enabled to allow th e recovery. although this oscillator runs at a much slower speed th an the original system clock, the cpu contin- ues to operate, allowing execution of a cloc k failure vector and software routines that either remedy the oscillator failure or issue a failure alert. this au tomatic switch-over is not available if the watch-dog timer is selected as the system clock oscillator. it is also unavailable if the watch-dog timer oscillator is disabled, though it is not necessary to enable the watch-dog timer reset function ou tlined in the watch-dog timer chapter of this document on page 83 . the primary oscillator failure detection circ uitry asserts if the system clock frequency drops below 1khz 50%. if an external signal is selected as the system oscillator, it is possible that a very slow but non-failing cloc k can generate a failu re condition. under these conditions, do not enable the clock failure circuitry (s ofen must be deasserted in the oscctl register). watch-dog timer failure in the event of a watch-dog timer oscillator fa ilure, a similar non-maskable interrupt-like event is issued. this event does not trigger an attendant clock switch-over, but alerts the cpu of the failure. after a watch-dog timer failu re, it is no longer possible to detect a primary oscillator failure. the failure detec tion circuitry does not function if the watch- dog timer is used as the syst em clock oscillator or if the watch-dog timer oscillator has been disabled. for either of these cases, it is necessary to disable the detection circuitry by deasserting the wdfen bit of the oscctl register. the watch-dog timer oscillator failure detectio n circuit counts system clocks while look- ing for a watch-dog timer clock. the logic co unts 8004 system clock cycles before deter- mining that a failure has occurred. the system clock rate determines the speed at which
ps022815-0206 oscillator control z8 encore! xp ? 4k series product specification 183 the watch-dog timer failure can be detected. a very slow system clock results in very slow detection times. it is possible to disable the clock failure de tection circuitry as we ll as all functioning clock sources. in this case, the z8 encore! xp ? 4k series device ceases functioning and can only be recovered by power-on-reset. oscillator control register definitions oscillator control register the oscillator control register (oscctl) enables/disables the various oscillator circuits, enables/disables the failure detection/recovery circuitry and selects the primary oscillator, which becomes th e system clock. the oscillator control register must be un locked before writing. writing the two step sequence e7h followed by 18h to the oscillator control regi ster unlocks it. the register is locked at successful completion of a register write to the oscctl. inten?internal precision oscillator enable 1 = internal precision oscillator is enabled 0 = internal precision oscillator is disabled xtlen?crystal oscillator enab le; this setting overrides the gpio register control for pa0 and pa1 1 = crystal oscillator is enabled 0 = crystal oscillator is disabled wdten?watchdog timer oscillator enable 1 = watch-dog timer oscillator is enabled 0 = watch-dog timer oscillator is disabled sofen?system clock oscillato r failure detection enable 1 = failure detection and recovery of system clock oscillator is enabled 0 = failure detection and recovery of system clock oscillator is disabled table 112. oscillator c ontrol register (oscctl) bits 7 6 5 4 3 2 1 0 field inten xtlen wdten sofen wdfen scksel reset 10100000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f86h caution:
ps022815-0206 oscillator control z8 encore! xp ? 4k series product specification 184 wdfen?watchdog timer oscillato r failure detection enable 1 = failure detection of watch- dog timer oscillator is enabled 0 = failure detection of watch- dog timer oscillator is disabled scksel?system clock oscillator select 000 = internal precision oscillator functions as system clock at 5.53 mhz 001 = internal precision oscillator functions as system clock at 32 khz 010 = crystal oscillator or external rc oscillator functions as system clock 011 = watch-dog timer oscillator functions as system 100 = external clock signal on pb3 functions as system clock 101 = reserved 110 = reserved 111 = reserved
ps022815-0206 crystal oscillator z8 encore! xp ? 4k series product specification 185 crystal oscillator overview the products in the z8 encore! xp ? 4k series contain an on-chip crystal oscillator for use with external crystals with 32 khz to 20 mhz frequencies. in addition, the oscillator sup- ports external rc networks with oscillation frequencies up to 4 mhz or ceramic resona- tors with frequencies up to 8mhz. the on-chip crystal oscillator can be used to generate the primary system clock for the internal ez8 cpu and the majority of the on-chip periph- erals. alternatively, the x in input pin can also accept a cmos -level clock input signal (32 khz?20 mhz). if an external clock generator is used, the x out pin must be left uncon- nected. the z8 encore! xp ? 4k series products do not contain an internal clock divider. the frequency of the signal on the x in input pin determines th e frequency of the system clock. although the xin pin can be used as an input for an external clock generator, the clkin pin is better suited for such use ( see system clock selection on page 180. ) operating modes the z8 encore! xp ? 4k series products support four oscillator modes: ? minimum power for use with very lo w frequency crystals (32 khz?1 mhz) ? medium power for use with medium fre quency crystals or ceramic resonators (0.5 mhz to 8 mhz) ? maximum power for use with high freque ncy crystals (8 mhz to 20 mhz) ? on-chip oscillator configured for use with external rc networks (<4 mhz) the oscillator mode is selected using user -programmable flash option bits. please refer to the chapter flash option bits on page 148 for information. crystal oscillator operation the flash option bit xtldis controls whethe r the crystal oscillator is enabled during reset. the crystal may later be disabled after reset if a new oscillato r has been selected as the system clock. if the crystal is manually enabled after reset through the oscctl regis- ter, the user code must wait at least 1000 cr ystal oscillator cycles for the crystal to stabi- lize. after this, the crystal oscillator may be selected as the system clock. note:
ps022815-0206 crystal oscillator z8 encore! xp ? 4k series product specification 186 the stabilization time will vary depending on the crystal or resonator used, as well as on the feedback network. see table 114 for transconductance valu es to compute oscillator stabilization times. figure 27 illustrates a recommended configuration for connection with an external funda- mental-mode, parallel-resonant crystal opera ting at 20 mhz. recommended 20 mhz crys- tal specifications are provided in table 113 . resistor r 1 is optional and limits total power dissipation by the crystal. printed circuit board layout must add no more than 4 pf of stray capacitance to either the x in or x out pins. if oscillation does not occur, reduce the values of capacitors c 1 and c 2 to decrease loading. figure 27.recommended 20 mhz crystal oscillator configuration table 113. recommended crystal oscillator specifications parameter value units comments frequency 20 mhz resonance parallel mode fundamental series resistance (r s ) 60 w maximum note: c2 = 15pf c1 = 15pf crystal xout xin on-chip oscillator
ps022815-0206 crystal oscillator z8 encore! xp ? 4k series product specification 187 note: * printed circuit board layout should not add more than 4 pf of stray capacitance to either xin or xout pins. if no oscillation occurs, reduce the values of the capacitors c1 and c2 to decrease the loading. oscillator operation with an external rc network figure 28 illustrates a recommended configuration for connection with an external resis- tor-capacitor (rc) network. load capacitance (c l )30 pf maximum shunt capacitance (c 0 ) 7 pf maximum drive level 1 mw maximum table 114. transconductance values for low, medium, and high gain operating modes mode crystal frequence range function transconductance (ma/v) use this range for calculations low gain (see note) 32 khz - 1 mhz low power/frequency applications 0.02 0.04 0.09 medium gain (see note) 0.5 mhz - 10 mhz medium power/frequency applications 0.84 1.7 3.1 high gain (see note) 8 mhz - 20 mhz high power/frequency applications 1.1 2.3 4.2 table 113. recommended crystal oscillator specifications parameter value units comments
ps022815-0206 crystal oscillator z8 encore! xp ? 4k series product specification 188 figure 28.connecting the on-chip oscillator to an external rc network an external resistance value of 45 k is recommended for osc illator operation with an external rc network. the minimum resistan ce value to ensure operation is 40 k . the typical oscillator frequency can be estimat ed from the values of the resistor ( r in k ) and capacitor ( c in pf) elements usi ng the following equation: figure 29 illustrates the typical (3.3 v and 25 0 c) oscillator frequency as a function of the capacitor ( c in pf) employed in the rc network assuming a 45 k external resistor. for very small values of c, the pa rasitic capacitance of the osc illator xin pin and the printed circuit board should be included in th e estimation of the oscillator frequency. it is possible to operate the rc oscillator usin g only the parasitic ca pacitance of the pack- age and printed circuit board. to minimize sensitivity to external parasitics, external capacitance values in excess of 20 pf are recommended. c x in r vdd oscillator frequency (khz) 1 6 10 0.4 rc () 4 c () + -------------------- ---------------------- ---------------- =
ps022815-0206 crystal oscillator z8 encore! xp ? 4k series product specification 189 figure 29.typical rc oscillator frequency as a function of the external capacitance with a 45kohm resistor when using the external rc oscillato r mode, the oscillator can stop oscil- lating if the power supply drops belo w 2.7v, but before the power supply drops to the voltage brown-out thres hold. the oscillator resumes oscilla- tion when the supply voltage exceeds 2.7v. 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500 c (pf) frequency (khz) caution:
ps022815-0206 internal precision oscillator z8 encore! xp ? 4k series product specification 190 internal precision oscillator overview the internal precision oscillator (ipo) is de signed for use without external components. the user can either manually trim the osc illator for a non-standard frequency or use the automatic factory-trimmed version to achieve a 5.53 mhz frequency. ipo features include: ? on-chip rc oscillator that does not require external components ? output frequency of either 5.53 mhz or 32.8 khz (contains both a fast and a slow mode) ? trimmed through flash option bits with user override ? elimination of crystals or cera mic resonators in applications where very high timing accu- racy is not required. operation an 8-bit trimming register, incorporated into the design, compensates for absolute varia- tion of oscillator frequency. once trimmed the o scillator frequency is stable and does not require subsequent calibration. trimming is performed during manufacturing and is not necessary for the user to repeat unless a fre quency other than 5.53 mhz (fast mode) or 32.8 khz (slow mode) is required. this trimming is done at +30oc and a supply voltage of 3.3 v, so accuracy of this operating point will be optimal. if not used, the ipo can be disabled by the oscillator control register ( page 183 ). by default, the oscillator frequency is set by the factory trim value stored in the write-pro- tected flash information page. however, the u ser code can override these trim values as described in trim bit address space on page 153 . select one of two frequencies for the oscillator: 5.53 mhz and 32.8 khz, using the osc- sel bits in the oscillator control on page 180 .
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 191 ez8 cpu instruction set assembly language programming introduction the ez8 cpu assembly language provides a me ans for writing an application program without concern for actual memory addresses or machine instruction formats. a program written in assembly language is called a sour ce program. assembly language allows the use of symbolic addresses to identify memory locations. it also allows mnemonic codes (opcodes and operands) to represent the inst ructions themselves. th e opcodes identify the instruction while the operands represent memo ry locations, registers, or immediate data values. each assembly language program consists of a series of symbolic commands called state- ments. each statement can contain labe ls, operations, operands and comments. labels can be assigned to a particular instru ction step in a source program. the label iden- tifies that step in the program as an entry point for use by other instructions. the assembly language also includes assembl er directives that supplement the machine instruction. the assembler directives, or p seudo-ops, are not transl ated into a machine instruction. rather, the pseudo-ops are interp reted as directives that control or assist the assembly process. the source program is processed (assembled) by the assembler to obtain a machine lan- guage program called the object code. the object code is executed by the ez8 cpu. an example segment of an assembly language pr ogram is detailed in the following example. assembly language source program example jp start ; everything after the semicolon is a comment. start: ; a label called ?start?. the first instruction ( jp start ) in this ; example causes program execution to jump to the point within the ; program where the start label occurs. ld r4, r7 ; a load (ld) instruction with two operands. the first operand, ; working register r4, is the de stination. the second operand, ; working register r7, is the so urce. the contents of r7 is ; written into r4. ld 234h, #%01 ; another load (ld) instruction with two operands. ; the first operand, extended mode register address 234h , ; identifies the destination. the second operand, immediate data ; value 01h , is the source. the value 01h is written into the ; register at address 234h .
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 192 assembly language syntax for proper instruction execution, ez8 cpu ass embly language syntax requires that the operands be written as ?destination, source?. af ter assembly, the obj ect code usually has the operands in the order ?source, destination? , but ordering is opcode-dependent. the fol- lowing instruction examples illust rate the format of some ba sic assembly instructions and the resulting object code produced by the assembler. this binary format must be followed by users that prefer manual program coding or intend to implement their own assembler. example 1 : if the contents of registers 43h and 08h are added and the result is stored in 43h, the assembly syntax and resulting object code is: example 2 : in general, when an instruction format requires an 8-bit register address, that address can specify any regist er location in the range 0?255 or, using escaped mode addressing, a working register r0?r15. if th e contents of register 43h and working register r8 are added and the result is stor ed in 43h, the assembl y syntax and resulting object code is: see the device-specific product specification to determine the exact register file range available. the register file size va ries, depending on the device type. ez8 cpu instruction notation in the ez8 cpu instruction summary and description sections, th e operands, condition codes, status flags, and addr ess modes are represented by a notational shorthand that is described in table 117 . table 115. assembly language syntax example 1 assembly language code add 43h, 08h (add dst, src) object code 04 08 43 (opc src, dst) table 116. assembly language syntax example 2 assembly language code add 43h, r8 (add dst, src) object code 04 e8 43 (opc src, dst)
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 193 . table 118 contains additional symbols that are us ed throughout the instruction summary and instruction set description sections. table 117. notational shorthand notation description operand range b bit b b represents a value from 0 to 7 (000b to 111b). cc condition code ? see condition codes overview in the ez8 cpu user manual. da direct address addrs addrs. represents a number in the range of 0000h to ffffh er extended addressing register reg reg. repr esents a number in the range of 000h to fffh im immediate data #data data is a number between 00h to ffh ir indirect working register @rn n = 0 ?15 ir indirect register @reg reg. represents a number in the range of 00h to ffh irr indirect working register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 irr indirect register pair @reg reg. represents an even number in the range 00h to feh p polarity p polarity is a single bit binary value of either 0b or 1b. r working register rn n = 0 ? 15 r register reg reg. represents a number in the range of 00h to ffh ra relative address x x represents an index in the range of +127 to ? 128 which is an offset relative to the address of the next instruction rr working register pair rrp p = 0, 2, 4, 6, 8, 10, 12, or 14 rr register pair reg reg. represents an even number in the range of 00h to feh vector vector address vector vector represents a number in the range of 00h to ffh x indexed #index the register or regist er pair to be indexed is offset by the signed index value (#index) in a +127 to -128 range.
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 194 assignment of a value is indicated by an arrow. for example, dst dst + src indicates the source data is added to the destin ation data and the result is stored in the des- tination location. ez8 cpu instruction classes ez8 cpu instructions can be divided fu nctionally into the following groups: ? arithmetic ? bit manipulation ? block transfer ? cpu control ? load ? logical ? program control ? rotate and shift table 118. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix sp stack pointer pc program counter flags flags register rp register pointer # immediate operand prefix b binary number suffix % hexadecimal number prefix h hexadecimal number suffix
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 195 tables 119 through 126 contain the instructions belong ing to each group and the number of operands required for each instruction. some inst ructions appear in more than one table as these instruction can be considered as a subs et of more than one category. within these tables, the source operand is identified as ?s rc?, the destination op erand is ?dst? and a con- dition code is ?cc?. table 119. arithmetic instructions mnemonic operands instruction adc dst, src add with carry adcx dst, src add with carry using extended addressing add dst, src add addx dst, src add using extended addressing cp dst, src compare cpc dst, src compare with carry cpcx dst, src compare with carry using extended addressing cpx dst, src compare using extended addressing da dst decimal adjust dec dst decrement decw dst decrement word inc dst increment incw dst increment word mult dst multiply sbc dst, src subtract with carry sbcx dst, src subtract with carry using extended addressing sub dst, src subtract subx dst, src subtract using extended addressing
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 196 table 120. bit manipulation instructions mnemonic operands instruction bclr bit, dst bit clear bit p, bit, dst bit set or clear bset bit, dst bit set bswap dst bit swap ccf ? complement carry flag rcf ? reset carry flag scf ? set carry flag tcm dst, src test complement under mask tcmx dst, src test complement under mask using extended addressing tm dst, src test under mask tmx dst, src test under mask using extended addressing table 121. block transfer instructions mnemonic operands instruction ldci dst, src load constant to/from program memory and auto-increment addresses ldei dst, src load external data to/from data memory and auto-increment addresses table 122. cpu control instructions mnemonic operands instruction atm ? atomic execution ccf ? complement carry flag di ? disable interrupts ei ? enable interrupts halt ? halt mode nop ? no operation rcf ? reset carry flag scf ? set carry flag srp src set register pointer
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 197 stop ? stop mode wdt ? watch-dog timer refresh table 123. load instructions mnemonic operands instruction clr dst clear ld dst, src load ldc dst, src load constant to/from program memory ldci dst, src load constant to/from program memory and auto-increment addresses lde dst, src load external data to/from data memory ldei dst, src load external data to/f rom data memory and auto-increment addresses ldwx dst, src load word using extended addressing ldx dst, src load using extended addressing lea dst, x(src) load effective address pop dst pop popx dst pop using extended addressing push src push pushx src push using extended addressing table 124. logical instructions mnemonic operands instruction and dst, src logical and andx dst, src logical and using extended addressing com dst complement or dst, src logical or orx dst, src logical or using extended addressing table 122. cpu control instructions mnemonic operands instruction
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 198 xor dst, src logical exclusive or xorx dst, src logical exclusive or using extended addressing table 125. program control instructions mnemonic operands instruction brk ? on-chip debugger break btj p, bit, src, da bit test and jump btjnz bit, src, da bit test and jump if non-zero btjz bit, src, da bit test and jump if zero call dst call procedure djnz dst, src, ra decrement and jump non-zero iret ? interrupt return jp dst jump jp cc dst jump conditional jr da jump relative jr cc da jump relative conditional ret ? return trap vector software trap table 126. rotate and shift instructions mnemonic operands instruction bswap dst bit swap rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic table 124. logical instructions mnemonic operands instruction
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 199 ez8 cpu instruction summary table 127 summarizes the ez8 cpu instructions . the table identifies the addressing modes employed by the instruction, the effect upon the flags register, the number of cpu clock cycles required for th e instruction fetch, and the number of cpu clock cycles required for the instruction execution. . srl dst shift right logical swap dst swap nibbles table 127. ez8 cpu instruction summary assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h adc dst, src dst dst + src + c r r 12 ****0* 2 3 rir 13 24 rr 14 3 3 rir 15 3 4 rim 16 3 3 ir im 17 3 4 adcx dst, src dst dst + src + c er er 18 ****0* 4 3 er im 19 4 3 add dst, src dst dst + src r r 02 ****0* 2 3 rir 03 24 rr 04 3 3 rir 05 3 4 rim 06 3 3 ir im 07 3 4 addx dst, src dst dst + src er er 08 ****0* 4 3 er im 09 4 3 flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1 table 126. rotate and shift instructions mnemonic operands instruction
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 200 and dst, src dst dst and src r r 52 ? * * 0 ? ? 2 3 rir 53 24 rr 54 3 3 rir 55 3 4 rim 56 3 3 ir im 57 3 4 andx dst, src dst dst and src er er 58 ? * * 0 ? ? 4 3 er im 59 4 3 atm block all interrupt and dma requests during execution of the next 3 instructions 2f ????? ? 1 2 bclr bit, dst dst[bit] 0re2?**0??22 bit p, bit, dst dst[bit] pre2?**0??22 brk debugger break 00 ? ? ? ? ? ? 1 1 bset bit, dst dst[bit] 1re2?**0??22 bswap dst dst[7:0] dst[0:7] r d5 x * * 0 ? ? 2 2 btj p, bit, src, dst if src[bit] = p pc pc + x r f6 ????? ? 3 3 ir f7 3 4 btjnz bit, src, dst if src[bit] = 1 pc pc + x r f6 ????? ? 3 3 ir f7 3 4 btjz bit, src, dst if src[bit] = 0 pc pc + x r f6 ????? ? 3 3 ir f7 3 4 call dst sp sp -2 @sp pc pc dst irr d4 ????? ? 2 6 da d6 3 3 ccf c ~c ef * ?????- 1 2 clr dst dst 00h r b0 ? ? ? ? ? ? 2 2 ir b1 2 3 table 127. ez8 cpu instruction summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 201 com dst dst ~dst r 60 ? * * 0 ? ? 2 2 ir 61 2 3 cp dst, src dst - src r r a2 ****?? 2 3 rir a3 24 rr a4 3 3 rir a5 3 4 rim a6 3 3 ir im a7 3 4 cpc dst, src dst - src - c r r 1f a2 ****?? 3 3 rir1f a3 34 rr1f a4 4 3 rir1f a5 4 4 rim1f a6 4 3 ir im 1f a7 4 4 cpcx dst, src dst - src - c er er 1f a8 ****?? 5 3 er im 1f a9 5 3 cpx dst, src dst - src er er a8 ****?? 4 3 er im a9 4 3 da dst dst da(dst) r 40 * * * x ? ? 2 2 ir 41 2 3 dec dst dst dst - 1 r 30 ?***?? 2 2 ir 31 2 3 decw dst dst dst - 1 rr 80 ?***?? 2 5 irr 81 2 6 di irqctl[7] 0 8f ????? ? 1 2 djnz dst, ra dst dst ? 1 if dst 0 pc pc + x r 0a-fa ????? ? 2 3 ei irqctl[7] 1 9f ????? ? 1 2 table 127. ez8 cpu instruction summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 202 halt halt mode 7f ? ? ? ? ? ? 1 2 inc dst dst dst + 1 r 20 ? * * ? ? ? 2 2 ir 21 2 3 r0e-fe 12 incw dst dst dst + 1 rr a0 ?***?? 2 5 irr a1 2 6 iret flags @sp sp sp + 1 pc @sp sp sp + 2 irqctl[7] 1 bf ***** * 1 5 jp dst pc dst da 8d ????? ? 3 2 irr c4 2 3 jp cc, dst if cc is true pc dst da 0d-fd ????? ? 3 2 jr dst pc pc + x da 8b ????? ? 2 2 jr cc, dst if cc is true pc pc + x da 0b-fb ????? ? 2 2 ld dst, rc dst src r im 0c-fc ? ? ? ? ? ? 2 2 r x(r) c7 3 3 x(r) r d7 3 4 rir e3 23 rr e4 3 2 rir e5 3 4 rim e6 3 2 ir im e7 3 3 ir r f3 2 3 ir r f5 3 3 table 127. ez8 cpu instruction summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 203 ldc dst, src dst src r irr c2 ????? ? 2 5 ir irr c5 2 9 irr r d2 2 5 ldci dst, src dst src r r + 1 rr rr + 1 ir irr c3 ????? ? 2 9 irr ir d3 2 9 lde dst, src dst src r irr 82 ????? ? 2 5 irr r 92 2 5 ldei dst, src dst src r r + 1 rr rr + 1 ir irr 83 ????? ? 2 9 irr ir 93 2 9 ldwx dst, src dst src er er 1fe8 ????? ? 5 4 ldx dst, src dst src r er 84 ????? ? 3 2 ir er 85 3 3 rirr 86 3 4 ir irr 87 3 5 r x(rr) 88 3 4 x(rr) r 89 3 4 er r 94 3 2 er ir 95 3 3 irr r 96 3 4 irr ir 97 3 5 er er e8 4 2 er im e9 4 2 lea dst, x(src) dst src + x r x(r) 98 ? ? ? ? ? ? 3 3 rr x(rr) 99 3 5 mult dst dst[15:0] dst[15:8] * dst[7:0] rr f4 ????? ? 2 8 nop no operation 0f ? ? ? ? ? ? 1 2 table 127. ez8 cpu instruction summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 204 or dst, src dst dst or src r r 42 ? * * 0 ? ? 2 3 rir 43 24 rr 44 3 3 rir 45 3 4 rim 46 3 3 ir im 47 3 4 orx dst, src dst dst or src er er 48 ? * * 0 ? ? 4 3 er im 49 4 3 pop dst dst @sp sp sp + 1 r 50 ????? ? 2 2 ir 51 2 3 popx dst dst @sp sp sp + 1 er d8 ????? ? 3 2 push src sp sp ? 1 @sp src r 70 ????? ? 2 2 ir 71 2 3 im if70 3 2 pushx src sp sp ? 1 @sp src er c8 ????? ? 3 2 rcf c 0 cf 0???? ? 1 2 ret pc @sp sp sp + 2 af ????? ? 1 4 rl dst r 90 ****?? 2 2 ir 91 2 3 rlc dst r 10 ****?? 2 2 ir 11 2 3 table 127. ez8 cpu instruction summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1 d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 205 rr dst r e0 ****?? 2 2 ir e1 2 3 rrc dst r c0 ****?? 2 2 ir c1 2 3 sbc dst, src dst dst ? src - c r r 32 ****1* 2 3 rir 33 24 rr 34 3 3 rir 35 3 4 rim 36 3 3 ir im 37 3 4 sbcx dst, src dst dst ? src - c er er 38 ****1* 4 3 er im 39 4 3 scf c 1 df 1???? ? 1 2 sra dst r d0 * * * 0 ? ? 2 2 ir d1 2 3 srl dst r 1f c0 * * 0 * ? ? 3 2 ir 1f c1 3 3 srp src rp src im 01 ????? ? 2 2 stop stop mode 6f ? ? ? ? ? ? 1 2 sub dst, src dst dst ? src r r 22 ****1* 2 3 rir 23 24 rr 24 3 3 rir 25 3 4 rim 26 3 3 ir im 27 3 4 table 127. ez8 cpu instruction summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1 d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c 0
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 206 subx dst, src dst dst ? src er er 28 ****1* 4 3 er im 29 4 3 swap dst dst[7:4] ? dst[3:0] r f0 x * * x ? ? 2 2 ir f1 2 3 tcm dst, src (not dst) and src r r 62 ? * * 0 ? ? 2 3 rir 63 24 rr 64 3 3 rir 65 3 4 rim 66 3 3 ir im 67 3 4 tcmx dst, src (not dst) and src er er 68 ? * * 0 ? ? 4 3 er im 69 4 3 tm dst, src dst and src r r 72 ? * * 0 ? ? 2 3 rir 73 24 rr 74 3 3 rir 75 3 4 rim 76 3 3 ir im 77 3 4 tmx dst, src dst and src er er 78 ? * * 0 ? ? 4 3 er im 79 4 3 trap vector sp sp ? 2 @sp pc sp sp ? 1 @sp flags pc @vector vector f2 ????? ? 2 6 wdt 5f ????? ? 1 2 table 127. ez8 cpu instruction summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps022815-0206 ez8 cpu instruction set z8 encore! xp ? 4k series product specification 207 xor dst, src dst dst xor src r r b2 ? * * 0 ? ? 2 3 rir b3 24 rr b4 3 3 rir b5 3 4 rim b6 3 3 ir im b7 3 4 xorx dst, src dst dst xor src er er b8 ? * * 0 ? ? 4 3 er im b9 4 3 table 127. ez8 cpu instruction summary (continued) assembly mnemonic symbol ic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src c z s v d h flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps022815-0206 opcode maps z8 encore! xp ? 4k series product specification 208 opcode maps a description of the opcode map data an d the abbreviations are provided in figure 30 . figures 31 and figure 32 provide information about each of the ez8 cpu instructions. table 128 lists opcode map abbreviations. figure 30.opcode map cell description cp 3.3 r2,r1 a 4 opcode lower nibble second operand after assembly first operand after assembly opcode upper nibble instruction cycles fetch cycles
ps022815-0206 opcode maps z8 encore! xp ? 4k series product specification 209 table 128. opcode map abbreviations abbreviation description a bbreviation description b bit position irr indirect register pair cc condition code p polarity (0 or 1) x 8-bit signed index or displacement r 4-bit working register da destination address r 8-bit register er extended addressing register r1, r1, ir1, irr1, ir1, rr1, rr1, irr1, er1 destination address im immediate data value r2, r2, ir2, irr2, ir2, rr2, rr2, irr2, er2 source address ir indirect working register ra relative ir indirect register rr working register pair irr indirect working register pair rr register pair
ps022815-0206 opcode maps z8 encore! xp ? 4k series product specification 210 figure 31.first opcode map cp 3.3 r2,r1 cp 3.4 ir2,r1 cp 2.3 r1,r2 cp 2.4 r1,ir2 cpx 4.3 er2,er1 cpx 4.3 im,er1 cp 3.3 r1,im cp 3.4 ir1,im rrc 2.2 r1 rrc 2.3 ir1 0 1 2 3 4 5 6 7 8 9abcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) brk 1.1 srp 2.2 im add 2.3 r1,r2 add 2.4 r1,ir2 add 3.3 r2,r1 add 3.4 ir2,r1 add 3.3 r1,im add 3.4 ir1,im addx 4.3 er2,er1 addx 4.3 im,er1 djnz 2.3 r1,x jr 2.2 cc,x ld 2.2 r1,im jp 3.2 cc,da inc 1.2 r1 nop 1.2 rlc 2.2 r1 rlc 2.3 ir1 adc 2.3 r1,r2 adc 2.4 r1,ir2 adc 3.3 r2,r1 adc 3.4 ir2,r1 adc 3.3 r1,im adc 3.4 ir1,im adcx 4.3 er2,er1 adcx 4.3 im,er1 inc 2.2 r1 inc 2.3 ir1 sub 2.3 r1,r2 sub 2.4 r1,ir2 sub 3.3 r2,r1 sub 3.4 ir2,r1 sub 3.3 r1,im sub 3.4 ir1,im subx 4.3 er2,er1 subx 4.3 im,er1 dec 2.2 r1 dec 2.3 ir1 sbc 2.3 r1,r2 sbc 2.4 r1,ir2 sbc 3.3 r2,r1 sbc 3.4 ir2,r1 sbc 3.3 r1,im sbc 3.4 ir1,im sbcx 4.3 er2,er1 sbcx 4.3 im,er1 da 2.2 r1 da 2.3 ir1 or 2.3 r1,r2 or 2.4 r1,ir2 or 3.3 r2,r1 or 3.4 ir2,r1 or 3.3 r1,im or 3.4 ir1,im orx 4.3 er2,er1 orx 4.3 im,er1 pop 2.2 r1 pop 2.3 ir1 and 2.3 r1,r2 and 2.4 r1,ir2 and 3.3 r2,r1 and 3.4 ir2,r1 and 3.3 r1,im and 3.4 ir1,im andx 4.3 er2,er1 andx 4.3 im,er1 com 2.2 r1 com 2.3 ir1 tcm 2.3 r1,r2 tcm 2.4 r1,ir2 tcm 3.3 r2,r1 tcm 3.4 ir2,r1 tcm 3.3 r1,im tcm 3.4 ir1,im tcmx 4.3 er2,er1 tcmx 4.3 im,er1 push 2.2 r2 push 2.3 ir2 tm 2.3 r1,r2 tm 2.4 r1,ir2 tm 3.3 r2,r1 tm 3.4 ir2,r1 tm 3.3 r1,im tm 3.4 ir1,im tmx 4.3 er2,er1 tmx 4.3 im,er1 decw 2.5 rr1 decw 2.6 irr1 lde 2.5 r1,irr2 ldei 2.9 ir1,irr2 ldx 3.2 r1,er2 ldx 3.3 ir1,er2 ldx 3.4 irr2,r1 ldx 3.5 irr2,ir1 ldx 3.4 r1,rr2,x ldx 3.4 rr1,r2,x rl 2.2 r1 rl 2.3 ir1 lde 2.5 r2,irr1 ldei 2.9 ir2,irr1 ldx 3.2 r2,er1 ldx 3.3 ir2,er1 ldx 3.4 r2,irr1 ldx 3.5 ir2,irr1 lea 3.3 r1,r2,x lea 3.5 rr1,rr2,x incw 2.5 rr1 incw 2.6 irr1 clr 2.2 r1 clr 2.3 ir1 xor 2.3 r1,r2 xor 2.4 r1,ir2 xor 3.3 r2,r1 xor 3.4 ir2,r1 xor 3.3 r1,im xor 3.4 ir1,im xorx 4.3 er2,er1 xorx 4.3 im,er1 ldc 2.5 r1,irr2 ldci 2.9 ir1,irr2 ldc 2.5 r2,irr1 ldci 2.9 ir2,irr1 jp 2.3 irr1 ldc 2.9 ir1,irr2 ld 3.4 r1,r2,x pushx 3.2 er2 sra 2.2 r1 sra 2.3 ir1 popx 3.2 er1 ld 3.4 r2,r1,x call 2.6 irr1 bswap 2.2 r1 call 3.3 da ld 3.2 r2,r1 ld 3.3 ir2,r1 bit 2.2 p,b,r1 ld 2.3 r1,ir2 ldx 4.2 er2,er1 ldx 4.2 im,er1 ld 3.2 r1,im ld 3.3 ir1,im rr 2.2 r1 rr 2.3 ir1 mult 2.8 rr1 ld 3.3 r2,ir1 trap 2.6 vector ld 2.3 ir1,r2 btj 3.3 p,b,r1,x btj 3.4 p,b,ir1,x swap 2.2 r1 swap 2.3 ir1 rcf 1.2 wdt 1.2 stop 1.2 halt 1.2 di 1.2 ei 1.2 ret 1.4 iret 1.5 scf 1.2 ccf 1.2 opcode see 2nd map 1, 2 atm
ps022815-0206 opcode maps z8 encore! xp ? 4k series product specification 211 figure 32.second opcode map after 1fh cpc 4.3 r2,r1 cpc 4.4 ir2,r1 cpc 3.3 r1,r2 cpc 3.4 r1,ir2 cpcx 5.3 er2,er1 cpcx 5.3 im,er1 cpc 4.3 r1,im cpc 4.4 ir1,im srl 3.2 r1 srl 3.3 ir1 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) 3, 2 push im ldwx 5, 4 er2,er1
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 212 electrical characteristics the data in this chapter is pre-qualificatio n and pre-characterization and is subject to change. additional electrical characteristics may be found in the individual chapters. absolute maximum ratings stresses greater than those listed in table 129 may cause permanent damage to the device. these ratings are stress ratings only. operation of the device at any condition outside those indicated in the operational s ections of these specifications is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. for improved reliability, tie unused in puts to one of the supply voltages (v dd or v ss ). table 129. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias -40 +105 c storage temperature -65 +150 c voltage on any pin with respect to v ss -0.3 +5.5 v 1 voltage on v dd pin with respect to v ss -0.3 +3.6 v maximum current on input and/or inactive output pin -5 +5 a maximum output current from active output pin -25 +25 ma 8-pin packages maximum ratings at 0c to 70c total power dissipation 220 mw maximum current into v dd or out of v ss 60 ma 20-pin packages maximum ratings at 0c to 70c total power dissipation 430 mw maximum current into v dd or out of v ss 120 ma 28-pin packages maximum ratings at 0c to 70c total power dissipation 450 mw maximum current into v dd or out of v ss 125 ma operating temperature is spec ified in dc characteristics 1. this voltage applies to all pins except the following: v dd , av dd , pins supporting analog input (port b[5:0], port c[2:0]) and pins supporting the crystal oscillator (pa0 and pa1). on the 8-pin packages, this applies to all pins but v dd .
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 213 dc characteristics table 130 lists the dc characteris tics of the z8 encore! xp ? 4k series products. all volt- ages are referenced to v ss , the primary system ground. table 130. dc characteristics symbol parameter t a = -40c to +105c (unless otherwise specified) units conditions minimum typical maximum v dd supply voltage 2.7 ? 3.6 v v il1 low level input voltage -0.3 ? 0.3*v dd v v ih1 high level input voltage 2.0 ? 5.5 v for all input pins without analog or oscillator f unction. for all signal pins on the 8-pin devices. programmable pull-ups must also be disabled. v ih2 high level input voltage 2.0 ? v dd +0.3 v for those pins with analog or oscillator function (20-/28-pin devices only), or when programmable pull-ups are enabled. v ol1 low level output voltage ??0.4vi ol = 2ma; v dd = 3.0v high output drive disabled. v oh1 high level output voltage 2.4 ? ? v i oh = -2ma; v dd = 3.0v high output drive disabled. v ol2 low level output voltage ??0.6vi ol = 20ma; v dd = 3.3v high output drive enabled. v oh2 high level output voltage 2.4 ? ? v i oh = -20ma; v dd = 3.3v high output drive enabled. i ih input leakage current ? + 0.002 + 5a i il input leakage current ? + 0.007 + 5a i led controlled current drive 1.8 3 4.5 ma {afs2,afs1} = {0,0} 2.8 7 10.5 ma {afs2,afs1} = {0,1} 7.8 13 19.5 ma {afs2,afs1} = {1,0} 12 20 30 ma {afs2,afs1} = {1,1} c pad gpio port pad capacitance ?8.0 2 ?pftbd c xin xin pad capacitance ? 8.0 2 ?pftbd
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 214 c xout xout pad capacitance ? 9.5 2 ?pftbd i pu weak pull-up current 30 100 350 a v dd = 3.0 - 3.6v v ram ram data retention voltage tbd v voltage at which ram will retain static values; no reading or writing is allowed. 1 this condition excludes all pins that have on-chip pull-ups, when driven low. 2 these values are provided for design guid ance only and are not tested in production. table 130. dc characteristics (continued) symbol parameter t a = -40c to +105c (unless otherwise specified) units conditions minimum typical maximum
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 215 table 131. power consumption symbol parameter v dd = 2.7v to 3.6v t a = 0c to +70c units conditions minimum typical 1 maximum i dd stop supply current in stop mode 1 a no peripherals enabled. all pins driven to v dd or v ss . i dd halt supply current in halt mode (with all peripherals disabled) 4a32 khz 520 a 5.5 mhz 1.9 ma 20 mhz i dd supply current in active mode 3.3 ma 32 khz 4.2 ma 5.5 mhz 4.9 ma 10 mhz 6.5 ma 20 mhz i dd wdt watchdog timer supply current 1a i dd xtal crystal oscillator supply current 40 a 32 khz 230 a 4 mhz 760 a 20 mhz i dd ipo internal precision oscillator supply current 1.5 ma i dd vbo voltage brown-out and low-voltage detect supply current 50 a for 20-/28-pin devices (vbo only); see note 2 for 8-pin devices; see note 2 i dd adc analog to digital converter supply current (with external reference) 2.8 ma 32 khz 3.0 ma 5.5 mhz 3.2 ma 10 mhz 3.5 ma 20 mhz i dd adcref adc inte rnal reference supply current 0 a see note 2 i dd cmp comparator supply current 100 a see note 2 i dd lpo low-power operational amplifier supply current 2 a driving a high-impedance load
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 216 figure 33 illustrates illustrates the typical curre nt consumption while operating with all peripherals disabled, at 30oc, ve rsus the system clock frequency. i dd ts temperature sensor supply current 60 a see note 2. i dd bg band gap supply current 310 a for 20-/28-pin devices for 8-pin devices 1 typical conditions are defined as vdd = 3.3v and +30 c . 2 for this block to operate, the bandgap circuit is automatically turned on and must be added to the total supply current. this bandgap current is only added once, regardless of how many peripherals are using it. figure 33. typical active mode i dd versus system clock frequency table 131. power consumption (continued) symbol parameter v dd = 2.7v to 3.6v t a = 0c to +70c units conditions minimum typical 1 maximum typical supply current - active mode 0 2 4 6 8 10 0 5 10 15 20 freq (mhz) idd (ma) vdd = 3.60v / 30c vdd = 3.30v / 30c vdd = 2.70v / 30c
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 217 ac characteristics the section provides information about the ac characteristics and timing. all ac timing information assumes a standard load of 50pf on all outputs. table 132. ac characteristics symbol parameter v dd = 2.7 to 3.6v t a = -40c to +105c (unless otherwise stated) units conditions minimum maximum f sysclk system clock frequency ? 20.0 mhz read-only from flash memory 0.032768 20.0 mhz program or erasure of the flash memory f xtal crystal oscillator frequency ? 20.0 mhz system clock frequencies below the crystal oscillator minimum require an external clock driver. t xin system clock period 50 ? ns t clk = 1/f sysclk t xinh system clock high time 20 30 ns t clk = 50ns t xinl system clock low time 20 30 ns t clk = 50ns t xinr system clock rise time ? 3 ns t clk = 50ns t xinf system clock fall time ? 3 ns t clk = 50ns
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 218 table 133. internal precision osci llator electrical characteristics symbol parameter v dd = 2.7 to 3.6v t a = -40c to +105c (unless otherwise stated) units conditions minimum typical maximum f ipo internal precision oscillator frequency (high speed) 5.53 v dd = 3.3v t a = 30c f ipo internal precision oscillator frequency (high speed) 5.31 5.53 5.75 mhz f ipo internal precision oscillator frequency (low speed) 30.7 32.7 33.3 khz t ipost internal precision oscillator startup time 0.7 s
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 219 on-chip peripheral ac and dc electrical characteristics table 134. power-on reset and voltage brown-out electrical characteristics and timing symbol parameter t a = -40c to +105c units conditions minimum typical 1 maximum v por power-on reset voltage threshold 2.20 2.45 2.70 v v dd = v por v vbo voltage brown-out reset voltage threshold 2.15 2.40 2.65 v v dd = v vbo v por to v vbo hysteresis 50 75 mv starting v dd voltage to ensure valid power-on reset. ?v ss ?v t ana power-on reset analog delay ?50 ?sv dd > v por ; t por digital reset delay follows t ana t por power-on reset digital delay 16 s 66 internal precision oscillator cycles + ipo startup time (t ipost ) t por power-on reset digital delay 1 ms 5000 internal precision oscillator cycles t smr stop mode recovery with crystal oscillator disabled 16 s 66 internal precision oscillator cycles t smr stop mode recovery with crystal oscillator enabled 1 ms 5000 internal precision oscillator cycles t vbo voltage brown-out pulse rejection period ?10 ? s v dd < v vbo to generate a reset. t ramp time for v dd to transition from v ss to v por to ensure valid reset 0.10 ? 100 ms t smp stop-mode recovery pin pulse rejection period 20 ns for any smr pin or for the reset pin when it is asserted in stop mode. 1 data in the typical co lumn is from characterization at 3.3v and 30 c. these values are provided for design guidance only and are not tested in production.
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 220 table 135. flash memory electrical characteristics and timing parameter v dd = 2.7 to 3.6v t a = -40c to +105c (unless otherwise stated) units notes minimum typical maximum flash byte read time 100 ? ? ns flash byte program time 20 ? 40 s flash page erase time 10 ? ? ms flash mass erase time 200 ? ? ms writes to single address before next erase ?? 2 flash row program time ? ? 8 ms cumulative program time for single row cannot exceed limit before next erase. this parameter is only an issue when bypassing the flash controller. data retention 100 ? ? years 25 c endurance 10,000 ? ? cycles program / erase cycles table 136. watch-dog timer electrical characteristics and timing symbol parameter v dd = 2.7 - 3.6v t a = -40c to +105c (unless otherwise stated) units conditions minimum typical maximum f wdt wdt oscillator frequency 5 10 15 khz t wdtcal wdt calibrated timeout 100 ms v dd = 3.3v; t a = 30c 100 ms v dd = 2.7v to 3.6v t a = 0c to 70c 100 ms v dd = 2.7v to 3.6v t a = -40c to +105c
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 221 table 137. non volatile data storage parameter v dd = 2.7 - 3.6v t a = -40c to +105c units notes minimum typical maximum nvds byte read time 34 ? 519 s with system clock at 20mhz nvds byte program time 0.171 ? 39.7 ms with system clock at 20mhz data retention 100 ? ? years 25 c endurance 160,000 ? ? cycles cumulative write cycles for entire memory table 138. analog-to-digital converter electrical characteristics and timing symbol parameter v dd = 3.0 to 3.6v t a = 0c to +70c units conditions minimum typical maximum resolution 10 ? bits differential nonlinearity (dnl) -1.0 ? 1.0 lsb 3 external v ref = 2.0v; r s 3.0k integral nonlinearity (inl) -3.0 ? 3.0 lsb 3 external v ref = 2.0v; r s 3.0k offset error with calibration + 1lsb 3 absolute accuracy with calibration + 3lsb 3 v ref internal reference voltage 1.0 2.0 1.1 2.2 1.2 2.4 v refsel=01 refsel=10 r refout reference buffer ouput impedance 850 when the internal reference is buffered and driven out to the vref pin (refout = 1) 1 analog source impedance affects the adc offset voltage (because of pin leakage) and input settling time. 2 devices are factory calibrated at v dd = 3.3v and t a = +30c, so the adc is maximally accurate under these conditions. 3 lsbs are defined assuming 10-bit resolution. 4 the input impedance is inversely proportional to the system clock frequency.
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 222 single-shot conversion time ? 5129 ? system clock cycles all measurements but temperature sensor 10258 temperature sensor measurement continuous conversion time ?256 ?system clock cycles all measurements but temperature sensor 512 temperature sensor measurement signal input bandwidth ? 10 khz as defined by -3db point r s analog source impedance ? ? 10 k in unbuffered mode 500 k in buffered modes zin input impedance tbd 150 k in unbuffered mode at 20mhz 4 10 tbd m in buffered modes vin input voltage range 0 v dd v unbuffered mode 0.3 v dd -1.1 v buffered modes note: these values define the range over which the adc performs within spec; exceeding these values does not cause damage or instability; see dc characteristics on page 213 for absolute pin voltage limits table 138. analog-to-digital converter electrical characteristics and timing symbol parameter v dd = 3.0 to 3.6v t a = 0c to +70c units conditions minimum typical maximum 1 analog source impedance affects the adc offset voltage (because of pin leakage) and input settling time. 2 devices are factory calibrated at v dd = 3.3v and t a = +30c, so the adc is maximally accurate under these conditions. 3 lsbs are defined assuming 10-bit resolution. 4 the input impedance is inversely proportional to the system clock frequency.
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 223 table 140. comparator electrical characteristics table 139. low power operational ampl ifer electrical characteristics symbol parameter v dd = 2.7 to 3.6v t a = -40c to +105c units conditions minimum typical maximum av open loop voltage gain 80 db gbw gain/bandwidth product 500 khz pm phase margin 53 deg assuming 13pf pin capacitance v oslpo input offset voltage ?4 4 mv v oslpo input offset voltage (temperature drift) 110 v/c over the range of -10 c to +40 c symbol parameter v dd = 2.7 to 3.6v t a = -40c to +105c units conditions minimum typical maximum v os input dc offset 5 mv v cref programmable internal reference voltage + 5 % 20-/28-pin devices + 3 % 8-pin devices t prop propagation delay 100 ns v hys input hysteresis 4 mv v in input voltage range v ss v dd -1 v
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 224 table 141. temperature sensor electrical characteristics general purpose i/o port input data sample timing figure 34 illustrates timing of the gpio port in put sampling. the inpu t value on a gpio port pin is sampled on the rising edge of the system clock. the port value is available to the ez8 cpu on the second rising clock edge following the change of the port value. symbol parameter v dd = 2.7 to 3.6v units conditions minimum typical maximum t aerr temperature error + 1.5 c over the range +20 c to +30 c (as measured by adc) c over the range +0 c to +70 c (as measured by adc) + 7 c over the range -40 c to +105 c (as measured by adc) t aerr temperature error tbd c over the range -40 c to +105 c (as measured by comparator) t wake wakeup time 80 100 us time required for temperature sensor to stabilize after enabling
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 225 figure 34. port input sample timing table 142. gpio port input timing parameter abbreviation delay (ns) minimum maximum t s_port port input transition to xin rise setup time (not pictured) 5? t h_port xin rise to port input transition hold time (not pictured) 0? t smr gpio port pin pulse width to ensure stop mode recovery (for gpio port pins enabled as smr sources) 1 s system tclk port pin port value changes to 0 0 latched into port input input value port input data register latch clock data register port input data read on data bus port input data register value 0 read by ez8
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 226 general purpose i/o port output timing figure 35 and table 143 provide timing information for gpio port pins. figure 35. gpio port output timing table 143. gpio port output timing parameter abbreviation delay (ns) minimum maximum gpio port pins t 1 xin rise to port output valid delay ? 15 t 2 xin rise to port output hold time 2 ? xin port output tclk t1 t2
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 227 on-chip debugger timing figure 36 and table 144 provide timing information for the dbg pin. the dbg pin tim- ing specifications assume a 4ns maximum rise and fall time. figure 36. on-chip debugger timing table 144. on-chip debugger timing parameter abbreviation delay (ns) minimum maximum dbg t 1 xin rise to dbg valid delay ? 15 t 2 xin rise to dbg output hold time 2 ? t 3 dbg to xin rise input setup time 5 ? t 4 dbg to xin rise input hold time 5 ? xin dbg tclk t1 t2 (output) dbg t3 t4 (input) output data input data
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 228 uart timing figure 37 and table 145 provide timing information for uart pins for the case where cts is used for flow control. the cts to de assertion delay (t1) assumes the transmit data register has been loaded with data prior to cts assertion. figure 37. uart timing with cts table 145. uart ti ming with cts parameter abbreviation delay (ns) minimum maximum uart t 1 cts fall to de output delay 2 * xin period 2 * xin period + 1 bit time t 2 de assertion to txd falling e dge (start bit) delay 5 t 3 end of stop bit(s) to de deassertion delay 5 cts de t1 (output) txd t2 (output) (input) start bit 0 bit 1 bit 7 parity stop end of stop bit(s) t3
ps022815-0206 electrical characteristics z8 encore! xp ? 4k series product specification 229 figure 38 and table 146 provide timing information for uart pins for the case where cts is not used for flow contro l. de asserts after the transmit data register has been writ- ten. de remains asserted for mu ltiple characters as long as the transmit data register is written with the next character before the current character has completed. figure 38. uart timing without cts table 146. uart timing without cts parameter abbreviation delay (ns) minimum maximum uart t 1 de assertion to txd falling ed ge (start bit) delay 1 * xin period 1 bit time t 2 end of stop bit(s) to de deassertion delay (tx data register is empty) 5 de t1 (output) txd t2 (output) start bit0 bit 1 bit 7 parity stop end of stop bit(s)
ps022815-0206 packaging z8 encore! xp ? 4k series product specification 230 packaging figure 39 illustrates the 8-pin plastic dual inlin e package (pdip) available for the z8 encore! xp ? 4k series devices. figure 39.8-pin plastic du al inline package (pdip) ea e b1 q1 b s a2 l e a1 c d e1 1 8 4 5 controlling dimensions : mm.
ps022815-0206 packaging z8 encore! xp ? 4k series product specification 231 figure 40 illustrates the 8-pin small outline integr ated circuit package (soic) available for the z8 encore! xp ? 4k series devices. figure 40. 8-pin small outline integrated circuit package (soic)
ps022815-0206 packaging z8 encore! xp ? 4k series product specification 232 figure 41 illustrates the 8-pin quad flat no-lead package (qfn)/ mlf-s available for the z8 encore! xp 4k series devices. this packag e has a footprint identical to that of the 8- pin soic, but with a lower profile. figure 41.8-pin quad flat no-lead package (qfn)/ mlf-s
ps022815-0206 packaging z8 encore! xp ? 4k series product specification 233 figure 42 illustrates the 20-pin plastic dual in line package (pdip) available for the z8 encore! xp ? 4k series devices. figure 42.20-pin plastic du al inline package (pdip)
ps022815-0206 packaging z8 encore! xp ? 4k series product specification 234 figure 43 illustrates the 20-pin small outline inte grated circuit package (soic) available for the z8 encore! xp ? 4k series devices. figure 43.20-pin small outline in tegrated circuit package (soic)
ps022815-0206 packaging z8 encore! xp ? 4k series product specification 235 figure 44 illustrates the 20-pin small shrink ou tline package (ssop) available for the z8 encore! xp ? 4k series devices. figure 44.20-pin small shrink outline package (ssop)
ps022815-0206 packaging z8 encore! xp ? 4k series product specification 236 figure 45 illustrates the 28-pin plastic dual in line package (pdip) available for the z8 encore! xp ? 4k series devices. figure 45.28-pin plastic du al inline package (pdip)
ps022815-0206 packaging z8 encore! xp ? 4k series product specification 237 figure 46 illustrates the 28-pin small outline integr ated circuit package (soic) available in the z8 encore! xp ? 4k series devices. figure 46.28-pin small outline in tegrated circuit package (soic)
ps022815-0206 packaging z8 encore! xp ? 4k series product specification 238 figure 47 illustrates the 28-pin small shrink ou tline package (ssop) available for the z8 encore! xp ? 4k series devices. figure 47.28-pin small shrink outline package (ssop) symbol a a1 b c a2 e millimeter inch min max min max 1.73 0.05 1.68 0.25 5.20 0.65 typ 0.09 10.07 7.65 0.63 1.86 0.0256 typ 0.13 10.20 1.73 7.80 5.30 1.99 0.21 1.78 0.75 0.068 0.002 0.066 0.010 0.205 0.004 0.397 0.301 0.025 0.073 0.005 0.068 0.209 0.006 0.402 0.307 0.030 0.078 0.008 0.070 0.015 0.212 0.008 0.407 0.311 0.037 0.38 0.20 10.33 5.38 7.90 0.95 nom nom d e h l controlling dimensions: mm leads are coplanar within .004 inches. h c detail a e d 28 15 114 seating plane a2 e a q1 a1 b l 0 - 8
ps022815-0206 ordering information z8 encore! xp ? 4k series product specification 239 ordering information part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description z8 encore! xp ? with 4kb flash, 10-bit analog-to-digital converter standard temperature: 0 to 70c z8f042apb020sc 4kb 1kb 128b 6 18 2 7 1 1 1 pdip 8-pin package z8f042aqb020sc 4kb 1kb 128b 6 18 2 7 1 1 1 qfn 8-pin package z8f042asb020sc 4kb 1kb 128b 6 18 2 7 1 1 1 soic 8-pin package z8f042ash020sc 4kb 1kb 128b 17 18 2 7 1 1 1 soic 20-pin package z8f042ahh020sc 4kb 1kb 128b 17 18 2 7 1 1 1 ssop 20-pin package z8f042aph020sc 4kb 1kb 128b 17 18 2 7 1 1 1 pdip 20-pin package z8f042asj020sc 4kb 1kb 128b 23 18 2 8 1 1 1 soic 28-pin package z8f042ahj020sc 4kb 1kb 128b 23 18 2 8 1 1 1 ssop 28-pin package z8f042apj020sc 4kb 1kb 128b 23 18 2 8 1 1 1 pdip 28-pin package extended temperature: -40 to 105c z8f042apb020ec 4kb 1kb 128b 6 18 2 7 1 1 1 pdip 8-pin package z8f042aqb020ec 4kb 1kb 128b 6 18 2 7 1 1 1 qfn 8-pin package z8f042asb020ec 4kb 1kb 128b 6 18 2 7 1 1 1 soic 8-pin package z8f042ash020ec 4kb 1kb 128b 17 18 2 7 1 1 1 soic 20-pin package z8f042ahh020ec 4kb 1kb 128b 17 18 2 7 1 1 1 ssop 20-pin package z8f042aph020ec 4kb 1kb 128b 17 18 2 7 1 1 1 pdip 20-pin package z8f042asj020ec 4kb 1kb 128b 23 18 2 8 1 1 1 soic 28-pin package z8f042ahj020ec 4kb 1kb 128b 23 18 2 8 1 1 1 ssop 28-pin package z8f042apj020ec 4kb 1kb 128b 23 18 2 8 1 1 1 pdip 28-pin package replace c with g for lead-free packaging
ps022815-0206 ordering information z8 encore! xp ? 4k series product specification 240 z8 encore! xp ? with 4kb flash standard temperature: 0 to 70c Z8F041Apb020sc 4kb 1kb 128b 6 18 2 0 1 1 0 pdip 8-pin package Z8F041Aqb020sc 4kb 1kb 128b 6 18 2 0 1 1 0 qfn 8-pin package Z8F041Asb020sc 4kb 1kb 128b 6 18 2 0 1 1 0 soic 8-pin package Z8F041Ash020sc 4kb 1kb 128b 17 18 2 0 1 1 0 soic 20-pin package Z8F041Ahh020sc 4kb 1kb 128b 17 18 2 0 1 1 0 ssop 20-pin package Z8F041Aph020sc 4kb 1kb 128b 17 18 2 0 1 1 0 pdip 20-pin package Z8F041Asj020sc 4kb 1kb 128b 25 18 2 0 1 1 0 soic 28-pin package Z8F041Ahj020sc 4kb 1kb 128b 25 18 2 0 1 1 0 ssop 28-pin package Z8F041Apj020sc 4kb 1kb 128b 25 18 2 0 1 1 0 pdip 28-pin package extended temperature: -40 to 105c Z8F041Apb020ec 4kb 1kb 128b 6 18 2 0 1 1 0 pdip 8-pin package Z8F041Aqb020ec 4kb 1kb 128b 6 18 2 0 1 1 0 pdip 8-pin package Z8F041Asb020ec 4kb 1kb 128b 6 18 2 0 1 1 0 soic 8-pin package Z8F041Ash020ec 4kb 1kb 128b 17 18 2 0 1 1 0 soic 20-pin package Z8F041Ahh020ec 4kb 1kb 128b 17 18 2 0 1 1 0 ssop 20-pin package Z8F041Aph020ec 4kb 1kb 128b 17 18 2 0 1 1 0 pdip 20-pin package Z8F041Asj020ec 4kb 1kb 128b 25 18 2 0 1 1 0 soic 28-pin package Z8F041Ahj020ec 4kb 1kb 128b 25 18 2 0 1 1 0 ssop 28-pin package Z8F041Apj020ec 4kb 1kb 128b 25 18 2 0 1 1 0 pdip 28-pin package replace c with g for lead-free packaging part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022815-0206 ordering information z8 encore! xp ? 4k series product specification 241 z8 encore! xp ? with 2kb flash, 10-bit analog-to-digital converter standard temperature: 0 to 70c z8f022apb020sc 2kb 512b 64b 6 18 2 7 1 1 1 pdip 8-pin package z8f022aqb020sc 2kb 512b 64b 6 18 2 7 1 1 1 qfn 8-pin package z8f022asb020sc 2kb 512b 64b 6 18 2 7 1 1 1 soic 8-pin package z8f022ash020sc 2kb 512b 64b 17 18 2 7 1 1 1 soic 20-pin package z8f022ahh020sc 2kb 512b 64b 17 18 2 7 1 1 1 ssop 20-pin package z8f022aph020sc 2kb 512b 64b 17 18 2 7 1 1 1 pdip 20-pin package z8f022asj020sc 2kb 512b 64b 23 18 2 8 1 1 1 soic 28-pin package z8f022ahj020sc 2kb 512b 64b 23 18 2 8 1 1 1 ssop 28-pin package z8f022apj020sc 2kb 512b 64b 23 18 2 8 1 1 1 pdip 28-pin package extended temperature: -40 to 105c z8f022apb020ec 2kb 512b 64b 6 18 2 7 1 1 1 pdip 8-pin package z8f022aqb020ec 2kb 512b 64b 6 18 2 7 1 1 1 qfn 8-pin package z8f022asb020ec 2kb 512b 64b 6 18 2 7 1 1 1 soic 8-pin package z8f022ash020ec 2kb 512b 64b 17 18 2 7 1 1 1 soic 20-pin package z8f022ahh020ec 2kb 512b 64b 17 18 2 7 1 1 1 ssop 20-pin package z8f022aph020ec 2kb 512b 64b 17 18 2 7 1 1 1 pdip 20-pin package z8f022asj020ec 2kb 512b 64b 23 18 2 8 1 1 1 soic 28-pin package z8f022ahj020ec 2kb 512b 64b 23 18 2 8 1 1 1 ssop 28-pin package z8f022apj020ec 2kb 512b 64b 23 18 2 8 1 1 1 pdip 28-pin package replace c with g for lead-free packaging part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022815-0206 ordering information z8 encore! xp ? 4k series product specification 242 z8 encore! xp ? with 2kb flash standard temperature: 0 to 70c z8f021apb020sc 2kb 512b 64b 6 18 2 0 1 1 0 pdip 8-pin package z8f021aqb020sc 2kb 512b 64b 6 18 2 0 1 1 0 qfn 8-pin package z8f021asb020sc 2kb 512b 64b 6 18 2 0 1 1 0 soic 8-pin package z8f021ash020sc 2kb 512b 64b 17 18 2 0 1 1 0 soic 20-pin package z8f021ahh020sc 2kb 512b 64b 17 18 2 0 1 1 0 ssop 20-pin package z8f021aph020sc 2kb 512b 64b 17 18 2 0 1 1 0 pdip 20-pin package z8f021asj020sc 2kb 512b 64b 25 18 2 0 1 1 0 soic 28-pin package z8f021ahj020sc 2kb 512b 64b 25 18 2 0 1 1 0 ssop 28-pin package z8f021apj020sc 2kb 512b 64b 25 18 2 0 1 1 0 pdip 28-pin package extended temperature: -40 to 105c z8f021apb020ec 2kb 512b 64b 6 18 2 0 1 1 0 pdip 8-pin package z8f021aqb020ec 2kb 512b 64b 6 18 2 0 1 1 0 qfn 8-pin package z8f021asb020ec 2kb 512b 64b 6 18 2 0 1 1 0 soic 8-pin package z8f021ash020ec 2kb 512b 64b 17 18 2 0 1 1 0 soic 20-pin package z8f021ahh020ec 2kb 512b 64b 17 18 2 0 1 1 0 ssop 20-pin package z8f021aph020ec 2kb 512b 64b 17 18 2 0 1 1 0 pdip 20-pin package z8f021asj020ec 2kb 512b 64b 25 18 2 0 1 1 0 soic 28-pin package z8f021ahj020ec 2kb 512b 64b 25 18 2 0 1 1 0 ssop 28-pin package z8f021apj020ec 2kb 512b 64b 25 18 2 0 1 1 0 pdip 28-pin package replace c with g for lead-free packaging part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022815-0206 ordering information z8 encore! xp ? 4k series product specification 243 z8 encore! xp ? with 1kb flash, 10-bit analog-to-digital converter standard temperature: 0 to 70c z8f012apb020sc 1kb 256b 16b 6 18 2 7 1 1 1 pdip 8-pin package z8f012aqb020sc 1kb 256b 16b 6 18 2 7 1 1 1 qfn 8-pin package z8f012asb020sc 1kb 256b 16b 6 18 2 7 1 1 1 soic 8-pin package z8f012ash020sc 1kb 256b 16b 17 18 2 7 1 1 1 soic 20-pin package z8f012ahh020sc 1kb 256b 16b 17 18 2 7 1 1 1 ssop 20-pin package z8f012aph020sc 1kb 256b 16b 17 18 2 7 1 1 1 pdip 20-pin package z8f012asj020sc 1kb 256b 16b 23 18 2 8 1 1 1 soic 28-pin package z8f012ahj020sc 1kb 256b 16b 23 18 2 8 1 1 1 ssop 28-pin package z8f012apj020sc 1kb 256b 16b 23 18 2 8 1 1 1 pdip 28-pin package extended temperature: -40 to 105c z8f012apb020ec 1kb 256b 16b 6 18 2 7 1 1 1 pdip 8-pin package z8f012aqb020ec 1kb 256b 16b 6 18 2 7 1 1 1 qfn 8-pin package z8f012asb020ec 1kb 256b 16b 6 18 2 7 1 1 1 soic 8-pin package z8f012ash020ec 1kb 256b 16b 17 18 2 7 1 1 1 soic 20-pin package z8f012ahh020ec 1kb 256b 16b 17 18 2 7 1 1 1 ssop 20-pin package z8f012aph020ec 1kb 256b 16b 17 18 2 7 1 1 1 pdip 20-pin package z8f012asj020ec 1kb 256b 16b 23 18 2 8 1 1 1 soic 28-pin package z8f012ahj020ec 1kb 256b 16b 23 18 2 8 1 1 1 ssop 28-pin package z8f012apj020ec 1kb 256b 16b 23 18 2 8 1 1 1 pdip 28-pin package replace c with g for lead-free packaging part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022815-0206 ordering information z8 encore! xp ? 4k series product specification 244 z8 encore! xp ? with 1kb flash standard temperature: 0 to 70c z8f011apb020sc 1kb 256b 16b 6 18 2 0 1 1 0 pdip 8-pin package z8f011aqb020sc 1kb 256b 16b 6 18 2 0 1 1 0 qfn 8-pin package z8f011asb020sc 1kb 256b 16b 6 18 2 0 1 1 0 soic 8-pin package z8f011ash020sc 1kb 256b 16b 17 18 2 0 1 1 0 soic 20-pin package z8f011ahh020sc 1kb 256b 16b 17 18 2 0 1 1 0 ssop 20-pin package z8f011aph020sc 1kb 256b 16b 17 18 2 0 1 1 0 pdip 20-pin package z8f011asj020sc 1kb 256b 16b 25 18 2 0 1 1 0 soic 28-pin package z8f011ahj020sc 1kb 256b 16b 25 18 2 0 1 1 0 ssop 28-pin package z8f011apj020sc 1kb 256b 16b 25 18 2 0 1 1 0 pdip 28-pin package extended temperature: -40 to 105c z8f011apb020ec 1kb 256b 16b 6 18 2 0 1 1 0 pdip 8-pin package z8f011aqb020ec 1kb 256b 16b 6 18 2 0 1 1 0 qfn 8-pin package z8f011asb020ec 1kb 256b 16b 6 18 2 0 1 1 0 soic 8-pin package z8f011ash020ec 1kb 256b 16b 17 18 2 0 1 1 0 soic 20-pin package z8f011ahh020ec 1kb 256b 16b 17 18 2 0 1 1 0 ssop 20-pin package z8f011aph020ec 1kb 256b 16b 17 18 2 0 1 1 0 pdip 20-pin package z8f011asj020ec 1kb 256b 16b 25 18 2 0 1 1 0 soic 28-pin package z8f011ahj020ec 1kb 256b 16b 25 18 2 0 1 1 0 ssop 28-pin package z8f011apj020ec 1kb 256b 16b 25 18 2 0 1 1 0 pdip 28-pin package replace c with g for lead-free packaging z8f04a28100kit 20 and 28-pin development kit part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022815-0206 ordering information z8 encore! xp ? 4k series product specification 245 z8f04a08100kit 8-pin development kit zusbsc0100zac usb smart cable accessory kit part number flash ram nvds i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda comparator temperature sensor description
ps022815-0206 ordering information z8 encore! xp ? 4k series product specification 246 part number suffix designations z8 f 04 2a s h 020 s c environmental flow: c = standard plastic packaging compound g = green plastic packaging compound temperature range (c): s = standard, 0 to 70 e = extended, -40 to +105 speed: 020 = 20mhz pin count: b = 8 h = 20 j = 28 package: h = ssop p = pdip q = qfn s = soic device type memory size: 04 = 4kb flash, 1kb ram, 128b nvds 02 = 2kb flash, 512b ram, 64b nvds 01 = 1kb flash, 256b ram, 32b nvds memory type: f = flash device family
ps022815-0206 ordering information z8 encore! xp ? 4k series product specification 247 precharacterization product the product represented by this document is newly introduced and zilog has not com- pleted the full characterization of the prod uct. the document states what zilog knows about this product at this time, but additi onal features or nonconformance with some aspects of the document might be found, either by zilog or its customers in the course of further application and charact erization work. in addition, zilog cautions that delivery might be uncertain at times, because of start-up yield issues. zilog, inc. 532 race street san jose, ca 95126 telephone (408) 558-8500 fax 408 558-8300 internet: www.zilog.com customer support for valuable informa tion about downloading other relevant documents or for hardware and software development tools, visit the zilog web site at www.zilog.com .
ps022815-0206 customer feedback form z8 encore! xp ? 4k series product specification 248 customer feedback form customer support if you experience any problems while opera ting this product, please check the zilog knowledge base: http://kb.zilog.co m/kb/okbmain.asp if you cannot find an answer or have further questions, please see the zilog technical support web page: http://support.zilog.com
z8 encore! xp ? 4k series product specification ps022815-0206 index 249 index symbols # 194 % 194 @ 194 numerics 10-bit adc 4 40-lead plastic dual-inline package 237, 238 a absolute maximum ratings 212 ac characteristics 217 adc 195 architecture 113 automatic power-down 114 block diagram 114 continuous conversion 116 control register 124, 126 control register definitions 124 data high byte register 127 data low bits register 127 electrical characteristics and timing 221 operation 114 single-shot conversion 115 adcctl register 124, 126 adcdh register 127 adcdl register 127 adcx 195 add 195 add - extended addressing 195 add with carry 195 add with carry - extended addressing 195 additional symbols 194 address space 13 addx 195 analog signals 10 analog-to-digital converter (adc) 113 and 197 andx 197 arithmetic instructions 195 assembly language programming 191 assembly language syntax 192 b b 194 b 193 baud rate generator, uart 99 bclr 196 binary number suffix 194 bit 196 bit 193 clear 196 manipulation instructions 196 set 196 set or clear 196 swap 196 test and jump 198 test and jump if non-zero 198 test and jump if zero 198 bit jump and test if non-zero 198 bit swap 198 block diagram 2 block transfer instructions 196 brk 198 bset 196 bswap 196, 198 btj 198 btjnz 198 btjz 198 c call procedure 198 capture mode 80, 81 capture/compare mode 80 cc 193 ccf 196 characteristics, electrical 212 clear 197 clr 197 com 197
z8 encore! xp ? 4k series product specification ps022815-0206 index 250 compare 80 compare - extended addressing 195 compare mode 80 compare with carry 195 compare with carry - extended addressing 195 complement 197 complement carry flag 196 condition code 193 continuous conversion (adc) 116 continuous mode 80 control register definition, uart 100 control registers 13, 16 counter modes 80 cp 195 cpc 195 cpcx 195 cpu and peripheral overview 4 cpu control instructions 196 cpx 195 customer feedback form 248 customer information 248 d da 193, 195 data memory 15 dc characteristics 213 debugger, on-chip 167 dec 195 decimal adjust 195 decrement 195 decrement and jump non-zero 198 decrement word 195 decw 195 destination operand 194 device, port availability 32 di 196 direct address 193 disable interrupts 196 djnz 198 dst 194 e ei 196 electrical characteristics 212 adc 221 flash memory and timing 220 gpio input data sample timing 224 watch-dog timer 220, 223 enable interrupt 196 er 193 extended addressing register 193 external pin reset 24 ez8 cpu features 4 ez8 cpu instruction classes 194 ez8 cpu instruction notation 192 ez8 cpu instruction set 191 ez8 cpu instruction summary 199 f fctl register 144, 150, 151 features, z8 encore! 1 first opcode map 210 flags 194 flags register 194 flash controller 4 option bit address space 151 option bit configuration - reset 148 program memory address 0000h 151 program memory address 0001h 152 flash memory 136 arrrangement 137 byte programming 142 code protection 140 configurations 136 control register definitions 144, 150 controller bypass 143 electrical characteristics and timing 220 flash control register 144, 150, 151 flash option bits 141 flash status register 145 flow chart 139 frequency high and low byte registers 147 mass erase 142
z8 encore! xp ? 4k series product specification ps022815-0206 index 251 operation 138 operation timing 140 page erase 142 page select register 145, 146 fps register 145, 146 fstat register 145 g gated mode 80 general-purpose i/o 32 gpio 4, 32 alternate functions 33 architecture 33 control register definitions 40 input data sample timing 224 interrupts 40 port a-c pull-up enable sub-registers 45, 46 port a-h address registers 41 port a-h alternate function sub-registers 42 port a-h control registers 42 port a-h data direction sub-registers 42 port a-h high drive enable sub-registers 44 port a-h input data registers 46 port a-h output control sub-registers 43 port a-h output data registers 47 port a-h stop mode recovery sub-registers 44 port availability by device 32 port input timing 225 port output timing 226 h h 194 halt 196 halt mode 30, 196 hexadecimal number prefix/suffix 194 i i2c 4 im 193 immediate data 193 immediate operand prefix 194 inc 195 increment 195 increment word 195 incw 195 indexed 193 indirect address prefix 194 indirect register 193 indirect register pair 193 indirect working register 193 indirect working register pair 193 infrared encoder/decoder (irda) 109 instruction set 191 instruction set, ez8 cpu 191 instructions adc 195 adcx 195 add 195 addx 195 and 197 andx 197 arithmetic 195 bclr 196 bit 196 bit manipulation 196 block transfer 196 brk 198 bset 196 bswap 196, 198 btj 198 btjnz 198 btjz 198 call 198 ccf 196 clr 197 com 197 cp 195 cpc 195 cpcx 195 cpu control 196 cpx 195 da 195 dec 195
z8 encore! xp ? 4k series product specification ps022815-0206 index 252 decw 195 di 196 djnz 198 ei 196 halt 196 inc 195 incw 195 iret 198 jp 198 ld 197 ldc 197 ldci 196, 197 lde 197 ldei 196 ldx 197 lea 197 load 197 logical 197 mult 195 nop 196 or 197 orx 197 pop 197 popx 197 program control 198 push 197 pushx 197 rcf 196 ret 198 rl 198 rlc 198 rotate and shift 198 rr 198 rrc 198 sbc 195 scf 196 sra 198 srl 199 srp 196 stop 197 sub 195 subx 195 swap 199 tcm 196 tcmx 196 tm 196 tmx 196 trap 198 watch-dog timer refresh 197 xor 198 xorx 198 instructions, ez8 classes of 194 interrupt control register 61 interrupt controller 50 architecture 50 interrupt assertion types 53 interrupt vectors and priority 53 operation 52 register definitions 54 software interrupt assertion 54 interrupt edge select register 60 interrupt request 0 register 54 interrupt request 1 register 55 interrupt request 2 register 56 interrupt return 198 interrupt vector listing 50 interrupts uart 97 ir 193 ir 193 irda architecture 109 block diagram 109 control register definitions 112 operation 109 receiving data 111 transmitting data 110 iret 198 irq0 enable high and low bit registers 57 irq1 enable high and low bit registers 58 irq2 enable high and low bit registers 59 irr 193 irr 193 j jp 198 jump, conditional, relative, and relative condi-
z8 encore! xp ? 4k series product specification ps022815-0206 index 253 tional 198 l ld 197 ldc 197 ldci 196, 197 lde 197 ldei 196, 197 ldx 197 lea 197 load 197 load constant 196 load constant to/from program memory 197 load constant with auto-increment addresses 197 load effective address 197 load external data 197 load external data to/from data memory and auto-increment addresses 196 load external to/from data memory and auto-in- crement addresses 197 load instructions 197 load using extended addressing 197 logical and 197 logical and/extended addressing 197 logical exclusive or 198 logical exclusive or/extended addressing 198 logical instructions 197 logical or 197 logical or/extended addressing 197 low power modes 29 m master interrupt enable 52 memory data 15 program 14 mode capture 80, 81 capture/compare 80 continuous 80 counter 80 gated 80 one-shot 79 pwm 80 modes 80 mult 195 multiply 195 multiprocessor mode, uart 95 n nop (no operation) 196 notation b 193 cc 193 da 193 er 193 im 193 ir 193 ir 193 irr 193 irr 193 p 193 r 193 r 193 ra 193 rr 193 rr 193 vector 193 x 193 notational shorthand 193 o ocd architecture 167 auto-baud detector/generator 170 baud rate limits 170 block diagram 167 breakpoints 172 commands 172 control register 177 data format 170 dbg pin to rs-232 interface 168 debug mode 169
z8 encore! xp ? 4k series product specification ps022815-0206 index 254 debugger break 198 interface 168 serial errors 171 status register 178 timing 227 ocd commands execute instruction (12h) 177 read data memory (0dh) 176 read ocd control register (05h) 174 read ocd revision (00h) 174 read ocd status register (02h) 174 read program counter (07h) 175 read program memory (0bh) 175 read program memory crc (0eh) 176 read register (09h) 175 read runtime counter (03h) 174 step instruction (10h) 177 stuff instruction (11h) 177 write data memory (0ch) 176 write ocd control register (04h) 174 write program counter (06h) 174 write program memory (0ah) 175 write register (08h) 175 on-chip debugger (ocd) 167 on-chip debugger signals 10 on-chip oscillator 185 one-shot mode 79 opcode map abbreviations 209 cell description 208 first 210 second after 1fh 211 operational description 20, 29, 32, 50, 62, 83, 89, 109, 113, 130, 134, 136, 148, 163, 167, 180, 185, 190 or 197 ordering information 239 orx 197 oscillator signals 10 p p 193 packaging 20-pin pdip 233, 234 20-pin ssop 235, 238 28-pin pdip 236 28-pin soic 237 8-pin pdip 230 8-pin soic 231 pdip 237, 238 part selection guide 2 pc 194 pdip 237, 238 peripheral ac and dc electrical characteristics 219 pin characteristics 11 pin descriptions 7 polarity 193 pop 197 pop using extended addressing 197 popx 197 port availability, device 32 port input timing (gpio) 225 port output timing, gpio 226 power supply signals 10 power-down, automatic (adc) 114 power-on and voltage brown-out electrical characteristics and timing 219 power-on reset (por) 22 program control instructions 198 program counter 194 program memory 14 push 197 push using extended addressing 197 pushx 197 pwm mode 80 pxaddr register 41 pxctl register 42 r r 193 r 193 ra register address 193 rcf 196 receive
z8 encore! xp ? 4k series product specification ps022815-0206 index 255 irda data 111 receiving uart data-interrupt-driven method 94 receiving uart data-polled method 93 register 193 adc control (adcctl) 124, 126 adc data high byte (adcdh) 127 adc data low bits (adcdl) 127 flash control (fctl) 144, 150, 151 flash high and low byte (ffreqh and freeql) 147 flash page select (fps) 145, 146 flash status (fstat) 145 gpio port a-h address (pxaddr) 41 gpio port a-h alternate function sub-regis- ters 43 gpio port a-h control address (pxctl) 42 gpio port a-h data direction sub-registers 42 ocd control 177 ocd status 178 uartx baud rate high byte (uxbrh) 106 uartx baud rate low byte (uxbrl) 106 uartx control 0 (uxctl0) 103, 106 uartx control 1 (uxctl1) 104 uartx receive data (uxrxd) 101 uartx status 0 (uxstat0) 101 uartx status 1 (uxstat1) 103 uartx transmit data (uxtxd) 100 watch-dog timer control (wdtctl) 28, 86, 131, 183 watch-dog timer reload high byte (wdth) 87 watch-dog timer reload low byte (wdtl) 88 watch-dog timer reload upper byte (wdtu) 87 register file 13 register pair 193 register pointer 194 reset and stop mode characteristics 21 and stop mode recovery 20 carry flag 196 sources 22 ret 198 return 198 rl 198 rlc 198 rotate and shift instuctions 198 rotate left 198 rotate left through carry 198 rotate right 198 rotate right through carry 198 rp 194 rr 193, 198 rr 193 rrc 198 s sbc 195 scf 196 second opcode map after 1fh 211 set carry flag 196 set register pointer 196 shift right arithmatic 198 shift right logical 199 signal descriptions 9 single-sho conversion (adc) 115 software trap 198 source operand 194 sp 194 sra 198 src 194 srl 199 srp 196 stack pointer 194 stop 197 stop mode 29, 197 stop mode recovery sources 25, 27 using a gpio port pin transition 26, 27 using watch-dog timer time-out 26 sub 195 subtract 195 subtract - extended addressing 195 subtract with carry 195
z8 encore! xp ? 4k series product specification ps022815-0206 index 256 subtract with carry - extended addressing 195 subx 195 swap 199 swap nibbles 199 symbols, additional 194 t tcm 196 tcmx 196 test complement under mask 196 test complement under mask - extended ad- dressing 196 test under mask 196 test under mask - extended addressing 196 timer signals 9 timers 62 architecture 62 block diagram 63 capture mode 70, 71, 80, 81 capture/compare mode 74, 80 compare mode 72, 80 continuous mode 64, 80 counter mode 65, 66 counter modes 80 gated mode 73, 80 one-shot mode 63, 79 operating mode 63 pwm mode 67, 69, 80 reading the timer count values 75 reload high and low byte registers 76 timer control register definitions 76 timer output signal operation 75 timers 0-3 control registers 78, 79 high and low byte registers 76, 77 tm 196 tmx 196 tools, hardware and software 247 transmit irda data 110 transmitting uart data-polled method 91 transmitting uart dat-interrupt-driven method 92 trap 198 u uart 4 architecture 89 baud rate generator 99 baud rates table 107 control register definitions 100 controller signals 9 data format 90 interrupts 97 multiprocessor mode 95 receiving data using interrupt-driven meth- od 94 receiving data using the polled method 93 transmitting data usin the interrupt-driven method 92 transmitting data using the polled method 91 x baud rate high and low registers 106 x control 0 and control 1 registers 103 x status 0 and status 1 registers 101, 103 uxbrh register 106 uxbrl register 106 uxctl0 register 103, 106 uxctl1 register 104 uxrxd register 101 uxstat0 register 101 uxstat1 register 103 uxtxd register 100 v vector 193 voltage brown-out reset (vbr) 23 w watch-dog timer approximate time-out delay 84 approximate time-out delays 83, 130, 134, 163, 180, 190 cntl 23
z8 encore! xp ? 4k series product specification ps022815-0206 index 257 control register 86, 131, 183 electrical characteristics and timing 220, 223 interrupt in noromal operation 84 interrupt in stop mode 85 operation 83, 130, 134, 163, 180, 190 refresh 84, 197 reload unlock sequence 85 reload upper, high and low registers 87 reset 24 reset in normal operation 85 reset in stop mode 85 time-out response 84 wdtctl register 28, 86, 131, 183 wdth register 87 wdtl register 88 working register 193 working register pair 193 wtdu register 87 x x 193 xor 198 xorx 198 z z8 encore! block diagram 2 features 1 part selection guide 2

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